Changes between Initial Version and Version 1 of newport/PCIe

01/05/2018 12:17:09 AM (2 years ago)
Tim Harvey

initial page


  • newport/PCIe

    v1 v1  
     3= Newport PCI/PCIe Support =
     4The CN80XX/CN81XX has three PEM's (PCI Express Interface) internally which are routed to MiniPCIe socket's depending on board and Bootloader configuration (see [wiki:newport#hwconfig hwconfig]).
     6CN80XX/CN81XX PEM Features:
     7* PCIe root complex (RC) support
     8* PCIe Specification v3.0 compliant
     9* dedicated reset pin per port/controller
     10* PCIe memory-space master support:
     11 - 256 separate 32bit windows available for direct core access to PCIe memory space in Switch Logic Interface Unit (SLI)
     12  * Programmable store merging
     13  * Regions can be combined to form up to a 40bit window
     14 - Direct core PCIe I/O space and configuration space request generation windows in SLI
     15 - ECAM support
     16* Dected PCIe support summary:
     17 - Max_Payload_Size up to 256 bytes
     18 - Readcompletion boundary of 128 bytes
     19 - ECRC implemented
     20 - MSI-X implemented for both SR-IOV and non-SR-IOV configurations
     21 - ASPM support for both L0s and L1 (DLM/PHY power might not be reduced in these states but the power consumed by the link partner may be)
     22 - Extended tag supported
     23 - Atomic operations (both 32bit and 64bit CAS, FADD and SWAP)
     26== PCI Throughput ==
     27The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0Gbits/sec) however this requires a higher co-processor speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 was made because it saves approximately 500mW of power consumption and the lack of Gen3 PCIe card availability.
     29By default Newport boards support PCI Gen2 (5.0Gbits/sec) and are backwards compatible with PCI Gen1 (2.5Gbits/sec).
     31If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GBits/sec) please contact
     33The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.
     37== PCIe Reset ==
     38PCI Reset signals (PERST#) are routed to the Mini-PCIe slots.
     40On the Newport boards each Mini-PCIe socket has its own dedicated PCI Reset (PERST#) signal.