Changes between Version 5 and Version 6 of newport/PCIe


Ignore:
Timestamp:
03/08/2019 05:32:33 PM (4 months ago)
Author:
Tim Harvey
Comment:

explain relationship between PCIe frequency and bitrate and add note about GW640x

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  • newport/PCIe

    v5 v6  
    3535[=#throughput]
    3636== PCIe Throughput ==
    37 The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0Gbits/sec) however this requires a higher co-processor speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 was made because it saves approximately 500mW of power consumption and the lack of Gen3 PCIe card availability.
     37The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0GT/sec or 6.4Gbps) however this requires a higher co-processor (SCLK) speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 (5.0GT/sec or 4Gbps) was made because it saves approximately 500mW of power consumption and the lack of Gen3 miniPCIe card availability.
    3838
    39 By default Newport boards support PCI Gen2 (5.0Gbits/sec) and are backwards compatible with PCI Gen1 (2.5Gbits/sec).
     39By default Newport boards support PCI Gen2 (5.0GHz/sec or 4Gbps) which is backwards compatible with PCI Gen1 (2.5GT/sec or 2Gbps).
    4040
    41 If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GBits/sec) please contact sales@gateworks.com.
     41If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GGT/sec or 6.4Gbps) please contact sales@gateworks.com. A resistor modification is required on the board to do move SCLK from 350MHz to 550Mhz.
     42
     43Note that the GW640x boards have a coprocessor clock running at 550MHz but still configure PCIe for Gen2 rates. Therefore on a GW640x you can modify the QLM-FREQ.N0.QLM* proprety in BDK device-tree file bdk/boards/gw6404.dtsi to specify 8000 MHz for Gen3.
    4244
    4345The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.