wiki:sbcrevisions

Gateworks Single Board Computers Revisions

This page is to describe the difference between hardware revisions.

Ventana Family

GW51xx

Revision A

Date: 04/19/2013

  • Initial release

Revision B

Date: 09/17/2013

  • Add VDD_HIGH to GSC analog input for voltage monitoring
  • Select GPS 4800 baud NMEA protocol by default
  • Reduce voltage drop for USB OTG VBUS
  • Adjust 5V boost converter feedback resistors for more accurate 5V
  • Add i.MX6 GPIO control of mini-PCIe WiFi? disable
  • Move mounting holes to match other Ventana boards
  • Improve HDMI and OTG connectors footprints
  • Modify JTAG route from a star to a daisy chain topology

Revision B.1

Date: 11/08/2013

  • Eliminate possible high input voltage on the switching supply enable input by removing unnecessary R34 pullup

Revision C

Date: 09/04/2014

  • Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
  • Connect GPS PPS signal to reserved pin 49 on Mini-PCIe socket through unloaded configuration resistor
  • Change GSC VDD_HIGH connection to include a divide-by-two resistive divider since voltage exceeds analog-to-digital converter 2.5V reference
  • Add GSC analog input option to DIO
  • Replace U15 input power supply to increase operating voltage range and improved manufacturability
  • Ground RTC XTAL input to eliminate noise causing pre-mature watchdog resets (see Errata HW7)

Revision D

Date: 03/05/2015

  • Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
  • Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
  • Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
  • Reduce PORJ pullup resistor value for faster rise time
  • Improve inductor footprints for improved manufacturability

Revision E.1

Date: 12/23/2015

  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
  • Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input

Revision F

Date: 10/17/2016:

  • Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
  • Replaced GbE crystal for increased lifespan

GW520x

Revision A

Date: 10/18/2013

  • Initial Release

Revision A.1

Date: 10/18/2013

  • Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance.

Revision B.1

Date: 1/30/2014

  • Add WiFi disable signal to all Mini-PCIe sockets through zero ohm resistors
  • Add optional load JST 1x2x2mm connector under the pushbutton switch
  • Add ability to route USB OTG to miniPCIe socket instead of front-panel via GPIO
  • Replace 2-pin tamper switch connector with 3-pin connector to support CAN Bus, RS485, TTL serial and tamper switch option
  • Add optional CAN Bus transceiver
  • Add optional RS485 transceiver
  • Add optional TTL serial bypass resistors
  • Add option for 3.3V and 5V power to one pin of the digital I/O connector through unloaded configuration resistors

Revision C.1

Date: 3/31/2015

  • Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
  • Replace 3.3V TVS arrays with 2.5V arrays for improved protection
  • Add 3.3V voltage translator to both 2.5V PCISKTx_RSTJ signals for increased voltage margin
  • Remove capacitor on tamper switch input to reduce switch debounce time constant
  • Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in
  • Connect I2C3 bus to the digital I/O connector through unloaded configuration resistors
  • Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets through unloaded configuration resistors
  • Add changes to support SOM application, (a) add CAN bus transceiver bypass resistors, (b) add RS232 transceiver bypass resistors, (c) add connector under uSD/SIM socket to support SD, USB, battery voltage, and reset, (d) add 2-pin power input connector
  • Add "USB" to PCIe socket silkscreen for clarification

Revision C.2

Date: 4/3/2015

  • Add 100 ohm differential PCIe clock termination resistor for improved PCIe clock compliance.

Revision D

Date: 2/18/2016

  • Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
  • Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
  • Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J11.5 as an option
  • Add optional GSC analog input to J4.1 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
  • Add optional 4-pin friction latching connector for micro-B OTG connector
  • Add optional OTG ID pulldown resistor to configure OTG port for host operation when optional 4-pin connector is loaded
  • Reduce PORJ pullup resistor value for faster rise time
  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Add processor watchdog support by connecting WDOG_B to PMIC PWRON input
  • Add support for UHS-1 MMC cards to run at their full speed capability
  • Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input
  • Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
  • Update SIM/uSD socket footprint and move 0.2mm closer to board edge for improved manufacturing
  • Move USB signals away from SIM/uSD mounting tab slot to improve fabrication processes

GW522x

Revision A

Date: 01/29/2015

  • Initial release

Revision A.1

Date: 04/21/2015

  • Improve PCIe clock termination

Revision B

Date: 04/29/2015

  • Reduce PORJ pullup resistor value for faster rise time
  • Improve PCIe clock termination
  • Add processor watchdog support by connecting WDOG_B to PMIC PWRON input (see Errata HW12)
  • Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)
  • Correct the SPI connector bottom side silkscreen pin labels

Revision C

Date: 07/22/2015

  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see Errata HW14)
  • Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
  • Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills

Revision D

Date: 01/04/2017:

  • Add wide range linear regulator for powering the GSC battery from the input voltage when board power is turned off to extend battery life
  • Add option for external GSC battery connector
  • Replaced GbE crystal for increased lifespan

Revision D.1

Date: 01/06/2017:

  • Add LDO output capacitor.

GW53xx

Revision A

Date: 12/17/2013

  • Initial revision

Revision A.1

Date: 12/17/2013

  • Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance

Revision B

Date: 12/05/2013

  • Add resistor load option for I2C support via DIO connector

Revision C

Date: 07/29/2015

  • Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
  • Improved RJ45 TVS arrays
  • Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
  • Remove capacitor on tamper switch input to reduce switch debounce time constant (see Errata HW4)
  • Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in (see Errata HW8)
  • Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets pin 49 through unloaded configuration resistors
  • Add optional GSC analog input to J10.4 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
  • Increase USB boost converter power to 1.6A max current (see Errata HW6)

Revision D

Date: 10/10/2014

  • Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
  • Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
  • Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default and audio connector as an option
  • Add option to bypass CAN bus transceiver to provide additional TTL UARt
  • Add option to bypass RS232 transceiver

Revision E

Date: 03/31/2015

  • Reduce PORJ pullup resistor value for faster rise time
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
  • Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see Errata HW14)
  • Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
  • Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)

Revision F

  • Improve 5V Boost Supply for powering CAN, HDMI, and LVDS. (see Resolves Errata HW18
  • Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
  • Improve voltage rails with larger traces and capacitors for greater stability when operating in LDO-Bypass mode
  • Improve USB host connector durability

GW54xx

Revision B

Date: 03/14/2013

  • Initial Revision

Revision C

Date: 07/16/2013

  • Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
  • Fix Analog Video input functionality (see Errata HW1)
  • Fix GPS Antenna Short Protection (see Errata HW2)
  • Replace MMA8451 accelerometer with FXOS8700 accelerometer/magnetometer
  • Replace GSP with Wi2Wi Wi2Wi W2SG0008i for improved functionality
  • Replace UART handshake with additional UART tx/rx and made previous hardware handshaking a resistor loading option

Revision D

Date: 01/13/2014

  • Add optional serial console bypass to the RS485 connector
  • Add PoE diodes to second Ethernet connector for increased functionality
  • Add i.MX6 GPIO control of mini-PCIe WiFi? disable
  • Add installed SIM card outline to silkscreen for ease of use

Revision E

Date: 6/28/2016:

  • Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
  • Connect GPS PPS signal to reserved pin 49 of J9 (Top right) and J10 (Bottomr left/center) Mini-PCIe sockets through unloaded configuration resistors as a build option
  • Add 3.3V voltage translator to miniPCIe socket PERST# signals for increased voltage margin
  • Unload capacitor C473 to resolve issue with off-board tamper signal (see Errata HW4)
  • Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
  • Add ability to bypass CAN transceiver through loadable resistors
  • Add ability to bypass UART2 RS232 transceiver through loadable resistors
  • Improved GPS Antenna short circuit fault monitoring by lowering trip threshold to allow for higher power active antennas
  • Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J28.5 as an option
  • Add 0 to 5V GSC analog input available via 3-byte register at 0x1A to previously unused J27.4 connector
  • Add resistor loading option to provide 3.3V to J16.3
  • Add resistor loading option to provide 5.0V to J16.4
  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Add processor watchdog support by connecting WDOG2_B to PMIC PWRON input (see Errata HW12)
  • Reduce PCIe clock jitter to GEN2 levels by routing clock generator output back to processor PCIe clock input (see Errata HW14)
  • Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)
  • Add a reset generator to improve signalling during board reset
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills for greater stability when operating in LDO-Bypass mode as well as supporting higher frequency processors
  • Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
  • Improve USB host connector durability
  • Add SPI support via J32 ((ECSPI2 SS0) (see SPI))

Revision E.1

Date: 6/29/2016:

  • Increase VDD_1P8 current flow with soldered wire

Revision F

Date: 11/01/2016:

  • Increase VDD_1P8 trace width to remove need for wire from Revision E.1

GW551x

Revision A.1

Date: 01/08/2015

  • Initial release

Revision B

Date: 02/18/2015

  • Move passives further from mounting holes
  • Increase spacing between the HDMI input and HDMI output connectors
  • Reduce PORJ pullup resistor value for faster rise time
  • Improve HDMI video input to allow YUV422 semi-planar input allowing 1080p@60Hz (see Errata HW9)
  • Fix USB OTG device mode (see Errata HW10)

Revision C

Date: 10/06/2016:

  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input (see [wiki:ventana/errata#hw12 Errata HW12)
  • Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
  • Adjust processor drive on CPU crystal for increased lifespan
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills

Revision C.1

Date: 02/10/2017:

  • Fix HS/CLK on HDMI Input

Revision D

Date: 03/02/2017:

  • Fix YUV422 semi-planar HDMI input to support 1080p60

GW552x

Revision A.2

Date: 11/19/2014

  • Initial release

Revision B

Date: 07/29/2015

  • Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
  • Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
  • Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
  • Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
  • move barrel jack to the opposite side of the power supply to eliminate interface between HDMI and barrel jack mating connectors
  • add software controllable USB switch to configure one of the panel USB ports for either host or device

Revision C

Date: 03/29/2016

  • Reduce PORJ pullup resistor value for faster rise time
  • Add series resistor between battery positive and reverse current diode for UL two level protection
  • Adjust processor drive on CPU crystal for increased lifespan
  • Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
  • Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
  • Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
  • Add resistor load option for SPI support via J8 ((ECSPI3 J8.1:SS0# J8.2:SCLK, J8.17:MOSI, J8.18:MISO see SPI))
  • Add resistor load option for I2C support via J8 ((I2C3: J8.17:SCL, J8.18:SDA))
  • Move battery to reduce heat impact on it's lifespan
  • Replace J8 10pin connector with 20pin connector

Revision C.1

Date: 10/18/2016

  • Replace J8 20pin connector with 10pin connector (20pin connector available as option)

GW553x

Revision B

Date: 08/30/2016

  • Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
  • Replace 2-pin connector with reset switch for standard product (2-pin connector is optional)
  • Replace 2-pin connector with user LED (2-pin connector is optional)

Laguna Family

GW2388

Please see GW2388 User Manual and view revision notes at the end.

Please contact support

Other SBC Families

Please contact support

Last modified 9 days ago Last modified on 06/19/17 10:31:27