Changes between Version 29 and Version 30 of FSA


Ignore:
Timestamp:
02/23/2026 10:24:00 PM (2 days ago)
Author:
Tim Harvey
Comment:

updated MAYA details

Legend:

Unmodified
Added
Removed
Modified

  • FSA

    v29 v30  
    717717}}}
    718718
    719 Thread details:
    720  * spidev using Open Thread Border Router which is part of the NXP Matter implementation
    721  * the M.2 card has an on-board I/O expander with an output that enables the SPI transmit buffer; you must drive this high for SPI to respond (likely defaulted low for compatibility as these are vendor-defined pins):
    722  * openthread:
     719Thread Examples:
     720 * The NXP IW612 running Open Thread Border Router via SPI
     721  - the M.2 card has an on-board I/O expander with an output that enables the SPI transmit buffer; you must drive this high for SPI to respond (likely defaulted low for compatibility as these are vendor-defined pins):
     722 * openthread-iwxxx (NXP has patches to OpenThread for IW612 support)
    723723{{{#!bash
    724724# install build tools
    725725apt update
    726726apt install -y build-essential git
    727 # clone repo
    728 git clone https://github.com/openthread/openthread
    729 cd openthread
    730 # build the spi-hdlc-adapter tool
    731 gcc tools/spi-hdlc-adapter/spi-hdlc-adapter.c -o spi-hdlc-adapter
    732 ./spi-hdlc-adapter -v /dev/spidev1.2
    733 # FSA2_GPIO2 (GPIO4_24) is W_DISABLE2# used as BT_18_4_RST
    734 # FSA2_ALERT (GPIO4_4) is SPI_INT
    735 echo 120 > /sys/class/gpio/export
    736 echo 100 > /sys/class/gpio/export
    737 ./spi-hdlc-adapter --gpio-res=/sys/class/gpio/gpio120 --gpio-int=/sys/class/gpio/gpio100 --spi-align-allowance=16 -v /dev/spidev1.2
    738 Cntl-C
    739 echo 120 > /sys/class/gpio/unexport
    740 echo 100 > /sys/class/gpio/unexport
    741 
    742 # build oc-cli
    743 apt-get --no-install-recommends install -y g++ lsb-release cmake ninja-build shellcheck
    744 # build POSIX CLI
    745 # FSA2_GPIO2 (GPIO4_24) is W_DISABLE2# used as BT_18_4_RST
    746 # FSA2_ALERT (GPIO4_4) is SPI_INT
    747 ./build/posix/src/posix/ot-cli -v -d3 'spinel+spi:///dev/spidev1.2?gpio-reset-device=/dev/gpiochip3&gpio-reset-line=24&gpio-int-device=/dev/gpiochip3&gpio-int-line=4&spi-mode=0&spi-speed=1000000&spi-reset-delay=0&spi-align-allowance=16'
    748 }}}
    749 
    750 device-tree for GW8201-A+GW7020+GW16FE0-A revision in FSA1 socket:
    751 {{{#!bash
     727# clone the meta-nxp-connectivity layer which contains patches
     728git clone https://github.com/nxp-imx/meta-nxp-connectivity.git
     729cd meta-nxp-connectivity.git
     730# clone openthread
     731git clone https://github.com/openthread/openthread openthread-iwxxx
     732cd openthread-iwxxx
     733# checkout the base version that NXP's patches apply to
     734git checkout d31bcee81230bd82764838c76c9f291ba64814dd
     735# apply NXP patches
     736for file in ../meta-nxp-openthread/recipes-openthread/openthread-iwxxx/files/otpatches-082-d31bcee/*.patch; do git apply "$file"; done
     737# download required toolchains
     738./script/bootstrap
     739# build
     740./script/cmake-build posix ./script/cmake-build posix \
     741 -DOT_APP_CLI=ON \
     742 -DOT_APP_NCP=OFF \
     743 -DOT_DAEMON=ON \
     744 -DOT_FTD=ON \
     745 -DOT_POSIX_RCP_SPI_BUS=ON
     746ls ./build/posix/src/posix/
     747# run the ot daemon
     748./meta-nxp-connectivity/openthread-iwxxx/build/posix/src/posix/ot-daemon -v -d7 'spinel+spi:///dev/spidev1.1?gpio-reset-device=/dev/gpiochip3&gpio-reset-line=24&gpio-int-device=/dev/gpiochip3&gpio-int-line=4&spi-mode=0&spi-speed=10000000&spi-reset-delay=500&spi-align-allowance=16&gpio-int-active-low=1&spi-cs-delay-us=10'
     749# check status (shows GPIO's being used and interrupts)
     750grep THREAD /sys/kernel/debug/gpio /proc/interrupts
     751# in another thread use ot-ctl to communicate with the daemon
     752./meta-nxp-connectivity/openthread-iwxxx/build/posix/src/posix/ot-ctl version
     753}}}
     754 * note the GPIO device and line number must be specified on in the URL for the spinel over SPI userspace driver. These GPIO's can very from board to board and socket to socket.
     755
     756device-tree overlays:
     757 * GW8101 + GW16FE0 in FSA1:
     758{{{#!bash
     759// SPDX-License-Identifier: (GPL-2.0+ OR MIT)                                   
     760/*                                                                             
     761 * Copyright 2026 Gateworks Corporation                                         
     762 *                                                                             
     763 * The u-blox MAYA M.2 on a GW16FE0 FSA to M.2 E-Key adapter on a GW81xx-2x:   
     764 *  - GPIO1_IO13__GPIO1_IO13    FSA1_GPIO1 W_DISABLE1# PD# (input to Maya)     
     765 *  - SAI2_TXFS__GPIO4_IO24     FSA1_GPIO2 W_DISABLE2# BT_15.4_RST (input to May
     766a)                                                                             
     767 *  - GPIO1_IO04__GPIO1_IO04    FSA1_GPIO3 N/C
     768 *  - SAI1_RXD2__GPIO4_IO04     FSA1_GPIO4 ALERT# / SPI_INT# (output from Maya)
     769 *  - UART3 (4-wire) used for Bluetooth
     770 *  - SDHC1 4-bit SDIO used for WiFi (up to SDR104 with 208MHz clock)
     771 *  - SPI2 used for 802.15.4 Thread radio
     772 *  - I2C3 has io-expander with some outputs to enable SPI
     773 *
     774 */
     775
     776#include <dt-bindings/gpio/gpio.h>
     777
     778#include <dt-bindings/clock/imx8mp-clock.h>
     779#include "imx8mp-pinfunc.h"
     780
     781/dts-v1/;
     782/plugin/;
     783
    752784/* Bluetooth */
    753785&uart3 {
    754         pinctrl-names = "default";
    755         pinctrl-0 = <&pinctrl_uart3>;
    756         /* reparent clock for up to 4mbd support */
    757         assigned-clocks = <&clk IMX8MP_CLK_UART3>;
    758         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
    759         uart-has-rtscts;
    760         status = "okay";
    761 
    762         bluetooth {
    763                 compatible = "nxp,88w8987-bt";
    764                 fw-init-baudrate = <3000000>;
    765         };
     786        pinctrl-names = "default";
     787        pinctrl-0 = <&pinctrl_uart3>;
     788        /* reparent clock for up to 4mbd support */
     789        assigned-clocks = <&clk IMX8MP_CLK_UART3>;
     790        assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
     791        uart-has-rtscts;
     792        status = "okay";
     793
     794        bluetooth {
     795                compatible = "nxp,88w8987-bt";
     796                fw-init-baudrate = <3000000>;
     797        };
    766798};
     799
    767800
    768801/* Thread */
    769802&ecspi2 {
    770         /* ublox MAYA in FSA1 (CS2) */
    771         spidev@2 {
    772                 reg = <2>;
     803        #address-cells = <1>;
     804        #size-cells = <0>;
     805
     806        /* ublox MAYA in FSA1 (CS1) */
     807        spidev@1 {
     808                pinctrl-names = "default";
     809                pinctrl-0 = <&pinctrl_fsa1_spi>;
     810                reg = <1>;
    773811                compatible = "lwn,bk4";
    774                 spi-max-frequency = <1000000>;
     812                spi-max-frequency = <25000000>;
    775813        };
    776 }
     814};
    777815
    778816/* I2C port expander */
    779 &fsa1_i2c {
     817&i2c3 {
     818        #address-cells = <1>;
     819        #size-cells = <0>;
     820
    780821        gpio@21 {
    781822                compatible = "nxp,pcal9554b";
    … …  
    787828                        "btthread_reset_in", "", "", "", "";
    788829
     830                /* must be enabled for SPI */
    789831                spien_hog {
    790832                        gpio-hog;
    … …  
    794836                };
    795837
     838                /* also connected to W_DISABLE2# BT_15.4_RST */
    796839                threadrst_hog {
    797840                        gpio-hog;
    798                         output-high;
     841                        input;
    799842                        gpios = <1 GPIO_ACTIVE_HIGH>;
    800843                        line-name = "thread_rst#";
    801844                };
    802 
    803                 wlanwake_hog {
     845        };
     846};
     847
     848&iomuxc {
     849        pinctrl_fsa1_spi: fsa1spigrp {
     850                fsl,pins = <
     851                        MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13     0x146
     852                        MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24      0x106
     853                        MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04      0x146
     854                >;
     855        };
     856
     857        pinctrl_uart3: uart3grp {
     858                fsl,pins = <
     859                        MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX    0x140
     860                        MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX    0x140
     861                        MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
     862                        MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS  0x140
     863                >;
     864        };
     865};
     866}}}
     867 * GW8201-A+GW7020+GW16FE0-A revision in FSA1 socket:
     868{{{#!bash
     869// SPDX-License-Identifier: (GPL-2.0+ OR MIT)                                   
     870/*                                                                             
     871 * Copyright 2026 Gateworks Corporation                                         
     872 *                                                                             
     873 * The u-blox MAYA M.2 on a GW16FE0 FSA to M.2 E-Key adapter on a GW82xx-2x:   
     874 *  - GPIO1_IO13__GPIO1_IO13    FSA1_GPIO1 W_DISABLE1# PD# (input to Maya)     
     875 *  - SAI2_TXFS__GPIO4_IO24     FSA1_GPIO2 W_DISABLE2# BT_15.4_RST (input to May
     876a)                                                                             
     877 *  - GPIO1_IO04__GPIO1_IO04    FSA1_GPIO3 N/C
     878 *  - SAI1_RXD2__GPIO4_IO04     FSA1_GPIO4 ALERT# / SPI_INT# (output from Maya)
     879 *  - UART3 (4-wire) used for Bluetooth
     880 *  - SDHC1 4-bit SDIO used for WiFi (up to SDR104 with 208MHz clock)
     881 *  - SPI2 used for 802.15.4 Thread radio
     882 *  - I2C3 has io-expander with some outputs to enable SPI
     883 *
     884 */
     885
     886#include <dt-bindings/gpio/gpio.h>
     887
     888#include <dt-bindings/clock/imx8mp-clock.h>
     889#include "imx8mp-pinfunc.h"
     890
     891/dts-v1/;
     892/plugin/;
     893
     894/* Bluetooth */
     895&uart3 {
     896        pinctrl-names = "default";
     897        pinctrl-0 = <&pinctrl_uart3>;
     898        /* reparent clock for up to 4mbd support */
     899        assigned-clocks = <&clk IMX8MP_CLK_UART3>;
     900        assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
     901        uart-has-rtscts;
     902        status = "okay";
     903
     904        bluetooth {
     905                compatible = "nxp,88w8987-bt";
     906                fw-init-baudrate = <3000000>;
     907        };
     908};
     909
     910
     911/* Thread */
     912&ecspi2 {
     913        #address-cells = <1>;
     914        #size-cells = <0>;
     915
     916        /* ublox MAYA in FSA2 (CS2) */
     917        spidev@2 {
     918                pinctrl-names = "default";
     919                pinctrl-0 = <&pinctrl_fsa2_spi>;
     920                reg = <2>;
     921                compatible = "lwn,bk4";
     922                spi-max-frequency = <25000000>;
     923        };
     924};
     925
     926/* I2C port expander */
     927&fsa1 {
     928        #address-cells = <1>;
     929        #size-cells = <0>;
     930
     931        gpio@21 {
     932                compatible = "nxp,pcal9554b";
     933                reg = <0x21>;
     934                gpio-controller;
     935                #gpio-cells = <2>;
     936                gpio-line-names =
     937                        "spien", "thread_rst#", "wake_wlan", "wake_btthread",
     938                        "btthread_reset_in", "", "", "", "";
     939
     940                /* must be enabled for SPI */
     941                spien_hog {
    804942                        gpio-hog;
    805                         output-low;
    806                         gpios = <2 GPIO_ACTIVE_HIGH>;
    807                         line-name = "wlan_wake#";
     943                        output-high;
     944                        gpios = <0 GPIO_ACTIVE_HIGH>;
     945                        line-name = "spien";
    808946                };
    809947
    810                 threadwake_hog {
    811                         gpio-hog;
    812                         output-low;
    813                         gpios = <3 GPIO_ACTIVE_HIGH>;
    814                         line-name = "thread_wake#";
    815                 };
    816 
    817                 threadrstin_hog {
     948                /* also connected to W_DISABLE2# BT_15.4_RST */
     949                threadrst_hog {
    818950                        gpio-hog;
    819951                        input;
    820                         gpios = <4 GPIO_ACTIVE_HIGH>;
    821                         line-name = "threadrstin";
     952                        gpios = <1 GPIO_ACTIVE_HIGH>;
     953                        line-name = "thread_rst#";
    822954                };
    823955        };
    … …  
    825957
    826958&iomuxc {
    827         pinctrl_uart3: uart3grp {
    828                 fsl,pins = <
    829                         MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX    0x140
    830                         MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX    0x140
     959        pinctrl_fsa2_spi: fsa2spigrp {
     960                fsl,pins = <
     961                        MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13     0x146
     962                        MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24      0x106
     963                        MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04      0x146
     964                >;
     965        };
     966
     967        pinctrl_uart3: uart3grp {
     968                fsl,pins = <
     969                        MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX    0x140
     970                        MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX    0x140
    831971                        MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
    832972                        MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS  0x140
    833                 >;
    834         };
     973                >;
     974        };
    835975};
    836976}}}