43 | | root@OpenWrt:/# cat /sys/kernel/debug/clk/clk_summary |
44 | | clock enable_cnt prepare_cnt rate accuracy phase |
45 | | ---------------------------------------------------------------------------------------- |
46 | | anaclk2 0 0 0 0 0 |
47 | | lvds2_in 0 0 0 0 0 |
48 | | anaclk1 0 0 0 0 0 |
49 | | lvds1_in 0 0 0 0 0 |
50 | | dummy 3 3 0 0 0 |
51 | | lvds2_sel 0 0 0 0 0 |
52 | | lvds2_gate 0 0 0 0 0 |
53 | | usbphy2_gate 1 1 0 0 0 |
54 | | usbphy1_gate 1 1 0 0 0 |
55 | | osc 7 7 24000000 0 0 |
56 | | cko2_sel 1 1 24000000 0 0 |
57 | | cko2_podf 1 1 24000000 0 0 |
58 | | cko2 1 1 24000000 0 0 |
59 | | cko 1 1 24000000 0 0 |
60 | | periph_clk2_sel 0 0 24000000 0 0 |
61 | | periph_clk2 0 0 24000000 0 0 |
62 | | gpt_3m 1 1 3000000 0 0 |
63 | | pll7_bypass_src 1 1 24000000 0 0 |
64 | | pll7 1 1 480000000 0 0 |
65 | | pll7_bypass 1 1 480000000 0 0 |
66 | | pll7_usb_host 1 1 480000000 0 0 |
67 | | usbphy2 1 1 480000000 0 0 |
68 | | pll6_bypass_src 1 1 24000000 0 0 |
69 | | pll6 1 1 500000000 0 0 |
70 | | pll6_bypass 1 1 500000000 0 0 |
71 | | pll6_enet 3 3 500000000 0 0 |
72 | | enet_ref 1 1 50000000 0 0 |
73 | | pcie_ref 1 1 125000000 0 0 |
74 | | pcie_ref_125m 1 1 125000000 0 0 |
75 | | sata_ref 1 1 100000000 0 0 |
76 | | sata_ref_100m 1 1 100000000 0 0 |
77 | | lvds1_sel 1 1 100000000 0 0 |
78 | | lvds1_gate 1 1 100000000 0 0 |
79 | | pll5_bypass_src 0 0 24000000 0 0 |
80 | | pll5 0 0 288000000 0 0 |
81 | | pll5_bypass 0 0 288000000 0 0 |
82 | | pll5_video 0 0 288000000 0 0 |
83 | | pll5_post_div 0 0 72000000 0 0 |
84 | | pll5_video_div 0 0 72000000 0 0 |
85 | | ipu2_di1_pre_sel 0 0 72000000 0 0 |
86 | | ipu2_di1_pre 0 0 24000000 0 0 |
87 | | ipu2_di1_sel 0 0 24000000 0 0 |
88 | | ipu2_di1 0 0 24000000 0 0 |
89 | | ipu2_di0_pre_sel 0 0 72000000 0 0 |
90 | | ipu2_di0_pre 0 0 24000000 0 0 |
91 | | ipu2_di0_sel 0 0 24000000 0 0 |
92 | | ipu2_di0 0 0 24000000 0 0 |
93 | | ipu1_di1_pre_sel 0 0 72000000 0 0 |
94 | | ipu1_di1_pre 0 0 24000000 0 0 |
95 | | ipu1_di1_sel 0 0 24000000 0 0 |
96 | | ipu1_di1 0 0 24000000 0 0 |
97 | | ipu1_di0_pre_sel 0 0 72000000 0 0 |
98 | | ipu1_di0_pre 0 0 24000000 0 0 |
99 | | pll4_bypass_src 0 0 24000000 0 0 |
100 | | pll4 0 0 144000000 0 0 |
101 | | pll4_bypass 0 0 144000000 0 0 |
102 | | pll4_audio 0 0 144000000 0 0 |
103 | | pll4_post_div 0 0 36000000 0 0 |
104 | | pll4_audio_div 0 0 36000000 0 0 |
105 | | pll3_bypass_src 1 1 24000000 0 0 |
106 | | pll3 1 1 480000000 0 0 |
107 | | pll3_bypass 1 1 480000000 0 0 |
108 | | pll3_usb_otg 4 5 480000000 0 0 |
109 | | ldb_di1_sel 0 0 480000000 0 0 |
110 | | ldb_di1_div_3_5 0 0 137142857 0 0 |
111 | | ldb_di1_podf 0 0 68571429 0 0 |
112 | | ldb_di1 0 0 68571429 0 0 |
113 | | ldb_di0_sel 0 0 480000000 0 0 |
114 | | ldb_di0_div_3_5 0 0 137142857 0 0 |
115 | | ldb_di0_podf 0 0 68571429 0 0 |
116 | | ldb_di0 0 0 68571429 0 0 |
117 | | ipu1_di0_sel 0 0 68571429 0 0 |
118 | | ipu1_di0 0 0 68571429 0 0 |
119 | | asrc_sel 0 0 480000000 0 0 |
120 | | asrc_pred 0 0 240000000 0 0 |
121 | | asrc_podf 0 0 30000000 0 0 |
122 | | asrc 0 0 30000000 0 0 |
123 | | esai_sel 0 0 480000000 0 0 |
124 | | esai_pred 0 0 240000000 0 0 |
125 | | esai_podf 0 0 30000000 0 0 |
126 | | esai_extal 0 0 30000000 0 0 |
127 | | periph2_clk2_sel 0 0 480000000 0 0 |
128 | | periph2_clk2 0 0 480000000 0 0 |
129 | | pll3_60m 0 1 60000000 0 0 |
130 | | ecspi_root 0 1 60000000 0 0 |
131 | | ecspi5 0 0 60000000 0 0 |
132 | | ecspi4 0 0 60000000 0 0 |
133 | | ecspi3 0 0 60000000 0 0 |
134 | | ecspi2 0 2 60000000 0 0 |
135 | | ecspi1 0 0 60000000 0 0 |
136 | | can_root 0 0 30000000 0 0 |
137 | | can2_serial 0 0 30000000 0 0 |
138 | | can1_serial 0 0 30000000 0 0 |
139 | | pll3_80m 1 1 80000000 0 0 |
140 | | uart_serial_podf 1 1 80000000 0 0 |
141 | | uart_serial 1 2 80000000 0 0 |
142 | | pll3_120m 0 0 120000000 0 0 |
143 | | pll3_pfd3_454m 0 0 454736842 0 0 |
144 | | spdif_sel 0 0 454736842 0 0 |
145 | | spdif_pred 0 0 227368421 0 0 |
146 | | spdif_podf 0 0 28421053 0 0 |
147 | | spdif 0 0 28421053 0 0 |
148 | | pll3_pfd2_508m 0 0 508235294 0 0 |
149 | | ssi3_sel 0 0 508235294 0 0 |
150 | | ssi3_pred 0 0 127058824 0 0 |
151 | | ssi3_podf 0 0 63529412 0 0 |
152 | | ssi3 0 0 63529412 0 0 |
153 | | ssi2_sel 0 0 508235294 0 0 |
154 | | ssi2_pred 0 0 127058824 0 0 |
155 | | ssi2_podf 0 0 63529412 0 0 |
156 | | ssi2 0 0 63529412 0 0 |
157 | | ssi1_sel 0 0 508235294 0 0 |
158 | | ssi1_pred 0 0 127058824 0 0 |
159 | | ssi1_podf 0 0 63529412 0 0 |
160 | | ssi1 0 0 63529412 0 0 |
161 | | pll3_pfd1_540m 1 1 540000000 0 0 |
162 | | video_27m 1 1 27000000 0 0 |
163 | | mipi_core_cfg 0 0 27000000 0 0 |
164 | | hdmi_isfr 1 1 27000000 0 0 |
165 | | pll3_pfd0_720m 0 0 720000000 0 0 |
166 | | gpu3d_shader_sel 0 0 720000000 0 0 |
167 | | gpu3d_shader 0 0 720000000 0 0 |
168 | | usbphy1 1 1 480000000 0 0 |
169 | | pll2_bypass_src 1 1 24000000 0 0 |
170 | | pll2 1 1 528000000 0 0 |
171 | | pll2_bypass 1 1 528000000 0 0 |
172 | | pll2_bus 2 2 528000000 0 0 |
173 | | cko1_sel 0 0 528000000 0 0 |
174 | | cko1_podf 0 0 528000000 0 0 |
175 | | cko1 0 0 528000000 0 0 |
176 | | periph2_pre 0 0 528000000 0 0 |
177 | | periph2 0 0 528000000 0 0 |
178 | | mmdc_ch1_axi_podf 0 0 528000000 0 0 |
179 | | mmdc_ch1_axi 0 0 528000000 0 0 |
180 | | periph_pre 1 1 528000000 0 0 |
181 | | periph 3 3 528000000 0 0 |
182 | | ahb 8 8 132000000 0 0 |
183 | | sdma 12 2 132000000 0 0 |
184 | | sata 1 1 132000000 0 0 |
185 | | rom 1 1 132000000 0 0 |
186 | | ocram 1 1 132000000 0 0 |
187 | | hdmi_iahb 1 1 132000000 0 0 |
188 | | esai_mem 0 0 132000000 0 0 |
189 | | esai_ipg 0 0 132000000 0 0 |
190 | | caam_aclk 1 1 132000000 0 0 |
191 | | caam_mem 1 1 132000000 0 0 |
192 | | asrc_mem 0 0 132000000 0 0 |
193 | | asrc_ipg 0 0 132000000 0 0 |
194 | | ipg 6 8 66000000 0 0 |
195 | | usboh3 2 2 66000000 0 0 |
196 | | uart_ipg 1 2 66000000 0 0 |
197 | | ssi3_ipg 0 0 66000000 0 0 |
198 | | ssi2_ipg 0 1 66000000 0 0 |
199 | | ssi1_ipg 0 1 66000000 0 0 |
200 | | spdif_gclk 0 0 66000000 0 0 |
201 | | spba 0 0 66000000 0 0 |
202 | | mipi_ipg 0 0 66000000 0 0 |
203 | | iim 0 0 66000000 0 0 |
204 | | gpt_ipg 1 1 66000000 0 0 |
205 | | enet 2 2 66000000 0 0 |
206 | | can2_ipg 0 0 66000000 0 0 |
207 | | can1_ipg 0 0 66000000 0 0 |
208 | | caam_ipg 1 1 66000000 0 0 |
209 | | ipg_per 1 1 66000000 0 0 |
210 | | pwm4 1 1 66000000 0 0 |
211 | | pwm3 0 0 66000000 0 0 |
212 | | pwm2 0 0 66000000 0 0 |
213 | | pwm1 0 0 66000000 0 0 |
214 | | i2c3 0 0 66000000 0 0 |
215 | | i2c2 0 0 66000000 0 0 |
216 | | i2c1 0 0 66000000 0 0 |
217 | | gpt_ipg_per 0 0 66000000 0 0 |
218 | | mmdc_ch0_axi_podf 1 1 528000000 0 0 |
219 | | mmdc_ch0_axi 3 3 528000000 0 0 |
220 | | ipu1_sel 1 1 528000000 0 0 |
221 | | ipu1_podf 1 1 264000000 0 0 |
222 | | ipu1 1 1 264000000 0 0 |
223 | | ipu2_sel 1 1 528000000 0 0 |
224 | | ipu2_podf 1 1 264000000 0 0 |
225 | | ipu2 1 1 264000000 0 0 |
226 | | axi_sel 1 1 528000000 0 0 |
227 | | axi 2 2 264000000 0 0 |
228 | | openvg_axi 0 0 264000000 0 0 |
229 | | mlb 0 0 264000000 0 0 |
230 | | gpu2d_axi 0 0 264000000 0 0 |
231 | | gpu3d_axi 0 0 264000000 0 0 |
232 | | pcie_axi_sel 1 1 264000000 0 0 |
233 | | pcie_axi 1 1 264000000 0 0 |
234 | | eim_slow_sel 1 1 264000000 0 0 |
235 | | eim_slow_podf 1 1 132000000 0 0 |
236 | | eim_slow 1 1 132000000 0 0 |
237 | | vdo_axi_sel 0 0 264000000 0 0 |
238 | | vdo_axi 0 0 264000000 0 0 |
239 | | vdoa 0 0 264000000 0 0 |
240 | | vpu_axi_sel 0 0 264000000 0 0 |
241 | | vpu_axi_podf 0 0 264000000 0 0 |
242 | | vpu_axi 0 0 264000000 0 0 |
243 | | pll2_pfd2_396m 1 1 396000000 0 0 |
244 | | eim_sel 0 0 396000000 0 0 |
245 | | eim_podf 0 0 198000000 0 0 |
246 | | enfc_sel 0 0 396000000 0 0 |
247 | | enfc_pred 0 0 99000000 0 0 |
248 | | enfc_podf 0 0 99000000 0 0 |
249 | | enfc 0 0 99000000 0 0 |
250 | | gpmi_io 0 0 99000000 0 0 |
251 | | usdhc4_sel 0 0 396000000 0 0 |
252 | | usdhc4_podf 0 0 198000000 0 0 |
253 | | usdhc4 0 0 198000000 0 0 |
254 | | gpmi_bch 0 0 198000000 0 0 |
255 | | usdhc3_sel 1 1 396000000 0 0 |
256 | | usdhc3_podf 1 1 198000000 0 0 |
257 | | usdhc3 4 4 198000000 0 0 |
258 | | apbh_dma 1 1 198000000 0 0 |
259 | | per1_bch 0 0 198000000 0 0 |
260 | | gpmi_bch_apb 0 0 198000000 0 0 |
261 | | gpmi_apb 0 0 198000000 0 0 |
262 | | usdhc2_sel 0 0 396000000 0 0 |
263 | | usdhc2_podf 0 0 198000000 0 0 |
264 | | usdhc2 0 0 198000000 0 0 |
265 | | usdhc1_sel 0 0 396000000 0 0 |
266 | | usdhc1_podf 0 0 198000000 0 0 |
267 | | usdhc1 0 0 198000000 0 0 |
268 | | hsi_tx_sel 0 0 396000000 0 0 |
269 | | hsi_tx_podf 0 0 198000000 0 0 |
270 | | hsi_tx 0 0 198000000 0 0 |
271 | | step 0 0 396000000 0 0 |
272 | | pll2_198m 0 0 198000000 0 0 |
273 | | pll2_pfd1_594m 0 0 594000000 0 0 |
274 | | gpu3d_core_sel 0 0 594000000 0 0 |
275 | | gpu3d_core_podf 0 0 594000000 0 0 |
276 | | gpu3d_core 0 0 594000000 0 0 |
277 | | pll2_pfd0_352m 0 0 352000000 0 0 |
278 | | gpu2d_core_sel 0 0 352000000 0 0 |
279 | | gpu2d_core_podf 0 0 352000000 0 0 |
280 | | gpu2d_core 0 0 352000000 0 0 |
281 | | pll1_bypass_src 1 1 24000000 0 0 |
282 | | pll1 1 1 996000000 0 0 |
283 | | pll1_bypass 1 1 996000000 0 0 |
284 | | pll1_sys 1 1 996000000 0 0 |
285 | | pll1_sw 1 1 996000000 0 0 |
286 | | arm 2 2 996000000 0 0 |
287 | | twd 1 1 498000000 0 0 |
288 | | ckih1 0 0 0 0 0 |
289 | | ckil 0 0 32768 0 0 |
290 | | root@OpenWrt:/# |
| 43 | root@mesh-10-2:~# cat /sys/kernel/debug/clk/clk_summary |
| 44 | enable prepare protect duty hardware |
| 45 | clock count count count rate accuracy phase cycle enable |
| 46 | ------------------------------------------------------------------------------------------------------- |
| 47 | sys_pll2 1 1 0 1000000000 0 0 50000 Y |
| 48 | sys_pll2_out 7 7 0 1000000000 0 0 50000 Y |
| 49 | sys_pll2_1000m 0 0 0 1000000000 0 0 50000 Y |
| 50 | disp_axi 0 0 0 500000000 0 0 50000 N |
| 51 | disp_axi_root_clk 0 0 0 500000000 0 0 50000 N |
| 52 | sys_pll2_500m 1 1 0 500000000 0 0 50000 Y |
| 53 | nand 0 0 0 500000000 0 0 50000 N |
| 54 | nand_root_clk 0 0 0 500000000 0 0 50000 N |
| 55 | usb_bus 2 2 0 500000000 0 0 50000 Y |
| 56 | usb1_ctrl_root_clk 1 1 0 500000000 0 0 50000 Y |
| 57 | sys_pll2_333m 1 1 0 333333333 0 0 50000 Y |
| 58 | main_axi 1 1 0 333333333 0 0 50000 Y |
| 59 | sys_pll2_250m 1 1 0 250000000 0 0 50000 Y |
| 60 | pcie1_ctrl 1 1 0 250000000 0 0 50000 Y |
| 61 | pcie1_root_clk 1 1 0 250000000 0 0 50000 Y |
| 62 | sys_pll2_200m 1 1 0 200000000 0 0 50000 Y |
| 63 | ecspi3 0 0 0 50000000 0 0 50000 N |
| 64 | ecspi3_root_clk 0 0 0 50000000 0 0 50000 N |
| 65 | ecspi2 1 1 0 50000000 0 0 50000 Y |
| 66 | ecspi2_root_clk 2 2 0 50000000 0 0 50000 Y |
| 67 | ecspi1 0 0 0 50000000 0 0 50000 N |
| 68 | ecspi1_root_clk 0 0 0 50000000 0 0 50000 N |
| 69 | arm_m4_core 0 0 0 200000000 0 0 50000 N |
| 70 | sys_pll2_166m 0 0 0 166666666 0 0 50000 Y |
| 71 | sys_pll2_125m 1 1 0 125000000 0 0 50000 Y |
| 72 | enet_ref 1 1 0 125000000 0 0 50000 Y |
| 73 | sys_pll2_100m 2 2 0 100000000 0 0 50000 Y |
| 74 | pcie1_phy 0 0 0 100000000 0 0 50000 N |
| 75 | gic 1 1 0 100000000 0 0 50000 Y |
| 76 | enet_timer 1 1 0 100000000 0 0 50000 Y |
| 77 | sys_pll2_50m 2 2 0 50000000 0 0 50000 Y |
| 78 | pcie1_aux 1 1 0 10000000 0 0 50000 Y |
| 79 | enet_phy 1 1 0 50000000 0 0 50000 Y |
| 80 | sys_pll1 1 1 0 800000000 0 0 50000 Y |
| 81 | sys_pll1_out 4 4 0 800000000 0 0 50000 Y |
| 82 | sys_pll1_800m 2 2 0 800000000 0 0 50000 Y |
| 83 | disp_apb 0 0 0 200000000 0 0 50000 N |
| 84 | disp_apb_root_clk 0 0 0 200000000 0 0 50000 N |
| 85 | vpu_bus 0 0 0 800000000 0 0 50000 N |
| 86 | vpu_dec_root_clk 0 0 0 800000000 0 0 50000 N |
| 87 | gpu_ahb 0 0 0 400000000 0 0 50000 N |
| 88 | gpu_axi 0 0 0 800000000 0 0 50000 N |
| 89 | gpu_root_clk 0 0 0 800000000 0 0 50000 N |
| 90 | audio_ahb 1 1 0 400000000 0 0 50000 Y |
| 91 | ipg_audio_root 1 2 0 400000000 0 0 50000 Y |
| 92 | sdma3_clk 0 2 0 400000000 0 0 50000 N |
| 93 | sdma2_clk 4 2 0 400000000 0 0 50000 Y |
| 94 | pdm_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 95 | sai6_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 96 | sai5_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 97 | sai4_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 98 | sai3_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 99 | sai2_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 100 | sai1_ipg_clk 0 0 0 400000000 0 0 50000 N |
| 101 | arm_a53_div 0 0 0 800000000 0 0 50000 N |
| 102 | dram_apb 1 1 0 160000000 0 0 50000 Y |
| 103 | sys_pll1_400m 0 0 0 400000000 0 0 50000 Y |
| 104 | usdhc3 0 0 0 400000000 0 0 50000 N |
| 105 | usdhc3_root_clk 0 0 0 400000000 0 0 50000 N |
| 106 | usdhc2 0 0 0 200000000 0 0 50000 N |
| 107 | usdhc2_root_clk 0 0 0 200000000 0 0 50000 N |
| 108 | usdhc1 0 0 0 200000000 0 0 50000 N |
| 109 | usdhc1_root_clk 0 0 0 200000000 0 0 50000 N |
| 110 | qspi 0 0 0 400000000 0 0 50000 N |
| 111 | qspi_root_clk 0 0 0 400000000 0 0 50000 N |
| 112 | sys_pll1_266m 2 2 0 266666666 0 0 50000 Y |
| 113 | nand_usdhc_bus 1 1 0 266666666 0 0 50000 Y |
| 114 | nand_usdhc_rawnand_clk 0 0 0 266666666 0 0 50000 N |
| 115 | enet_axi 1 1 0 266666666 0 0 50000 Y |
| 116 | enet1_root_clk 2 2 0 266666666 0 0 50000 Y |
| 117 | sys_pll1_200m 0 0 0 200000000 0 0 50000 Y |
| 118 | sys_pll1_160m 0 0 0 160000000 0 0 50000 Y |
| 119 | sys_pll1_133m 1 1 0 133333333 0 0 50000 Y |
| 120 | ahb 5 4 0 133333333 0 0 50000 Y |
| 121 | ipg_root 7 7 0 66666667 0 0 50000 Y |
| 122 | sdma1_clk 2 1 0 66666667 0 0 50000 Y |
| 123 | tmu_root_clk 1 1 0 66666667 0 0 50000 Y |
| 124 | ocotp_root_clk 0 0 0 66666667 0 0 50000 N |
| 125 | mu_root_clk 0 0 0 66666667 0 0 50000 N |
| 126 | gpio5_root_clk 1 1 0 66666667 0 0 50000 Y |
| 127 | gpio4_root_clk 1 1 0 66666667 0 0 50000 Y |
| 128 | gpio3_root_clk 0 0 0 66666667 0 0 50000 N |
| 129 | gpio2_root_clk 1 1 0 66666667 0 0 50000 Y |
| 130 | gpio1_root_clk 1 1 0 66666667 0 0 50000 Y |
| 131 | sys_pll1_100m 1 1 0 100000000 0 0 50000 Y |
| 132 | usb_phy_ref 1 1 0 100000000 0 0 50000 Y |
| 133 | dram_alt 0 0 0 100000000 0 0 50000 N |
| 134 | dram_alt_root 0 0 0 25000000 0 0 50000 Y |
| 135 | sys_pll1_80m 0 0 0 80000000 0 0 50000 Y |
| 136 | sys_pll1_40m 0 0 0 40000000 0 0 50000 Y |
| 137 | wrclk 0 0 0 40000000 0 0 50000 N |
| 138 | dummy 0 0 0 0 0 0 50000 Y |
| 139 | pcie0-refclk 2 2 0 100000000 0 0 50000 Y |
| 140 | clk_ext4 0 0 0 133000000 0 0 50000 Y |
| 141 | clk_ext3 0 0 0 133000000 0 0 50000 Y |
| 142 | clk_ext2 0 0 0 133000000 0 0 50000 Y |
| 143 | clk_ext1 0 0 0 133000000 0 0 50000 Y |
| 144 | osc_24m 7 11 0 24000000 0 0 50000 Y |
| 145 | gpt_3m 0 0 0 3000000 0 0 50000 Y |
| 146 | vpu_h1 0 0 0 24000000 0 0 50000 N |
| 147 | vpu_h1_root_clk 0 0 0 24000000 0 0 50000 N |
| 148 | pdm 0 0 0 24000000 0 0 50000 N |
| 149 | pdm_root_clk 0 0 0 24000000 0 0 50000 N |
| 150 | pcie2_aux 0 0 0 24000000 0 0 50000 N |
| 151 | pcie2_phy 0 0 0 24000000 0 0 50000 N |
| 152 | pcie2_ctrl 0 0 0 24000000 0 0 50000 N |
| 153 | csi2_esc 0 0 0 24000000 0 0 50000 N |
| 154 | csi2_phy_ref 0 0 0 24000000 0 0 50000 N |
| 155 | csi2_core 0 0 0 24000000 0 0 50000 N |
| 156 | csi1_esc 0 0 0 24000000 0 0 50000 N |
| 157 | csi1_phy_ref 0 0 0 24000000 0 0 50000 N |
| 158 | csi1_core 0 0 0 24000000 0 0 50000 N |
| 159 | csi1_root_clk 0 0 0 24000000 0 0 50000 N |
| 160 | dsi_dbi 0 0 0 24000000 0 0 50000 N |
| 161 | dsi_phy_ref 0 0 0 24000000 0 0 50000 N |
| 162 | dsi_core 0 0 0 24000000 0 0 50000 N |
| 163 | clko2 0 0 0 24000000 0 0 50000 N |
| 164 | clko1 0 0 0 24000000 0 0 50000 N |
| 165 | wdog 1 1 0 24000000 0 0 50000 Y |
| 166 | wdog3_root_clk 0 0 0 24000000 0 0 50000 N |
| 167 | wdog2_root_clk 0 0 0 24000000 0 0 50000 N |
| 168 | wdog1_root_clk 1 1 0 24000000 0 0 50000 Y |
| 169 | gpt1 0 0 0 24000000 0 0 50000 N |
| 170 | gpt1_root_clk 0 0 0 24000000 0 0 50000 N |
| 171 | pwm4 0 0 0 24000000 0 0 50000 N |
| 172 | pwm4_root_clk 0 0 0 24000000 0 0 50000 N |
| 173 | pwm3 0 0 0 24000000 0 0 50000 N |
| 174 | pwm3_root_clk 0 0 0 24000000 0 0 50000 N |
| 175 | pwm2 0 0 0 24000000 0 0 50000 N |
| 176 | pwm2_root_clk 0 0 0 24000000 0 0 50000 N |
| 177 | pwm1 0 0 0 24000000 0 0 50000 N |
| 178 | pwm1_root_clk 0 0 0 24000000 0 0 50000 N |
| 179 | usb_core_ref 0 0 0 24000000 0 0 50000 N |
| 180 | uart4 0 0 0 24000000 0 0 50000 N |
| 181 | uart4_root_clk 0 0 0 24000000 0 0 50000 N |
| 182 | uart3 0 0 0 24000000 0 0 50000 N |
| 183 | uart3_root_clk 0 0 0 24000000 0 0 50000 N |
| 184 | uart2 1 1 0 24000000 0 0 50000 Y |
| 185 | uart2_root_clk 4 4 0 24000000 0 0 50000 Y |
| 186 | uart1 0 0 0 24000000 0 0 50000 N |
| 187 | uart1_root_clk 0 0 0 24000000 0 0 50000 N |
| 188 | i2c4 0 0 0 24000000 0 0 50000 N |
| 189 | i2c4_root_clk 0 0 0 24000000 0 0 50000 N |
| 190 | i2c3 0 1 0 24000000 0 0 50000 N |
| 191 | i2c3_root_clk 0 1 0 24000000 0 0 50000 N |
| 192 | i2c2 0 1 0 24000000 0 0 50000 N |
| 193 | i2c2_root_clk 0 1 0 24000000 0 0 50000 N |
| 194 | i2c1 0 1 0 24000000 0 0 50000 N |
| 195 | i2c1_root_clk 0 1 0 24000000 0 0 50000 N |
| 196 | spdif2 0 0 0 24000000 0 0 50000 N |
| 197 | spdif1 0 0 0 24000000 0 0 50000 N |
| 198 | sai6 0 0 0 24000000 0 0 50000 N |
| 199 | sai6_root_clk 0 0 0 24000000 0 0 50000 N |
| 200 | sai5 0 0 0 24000000 0 0 50000 N |
| 201 | sai5_root_clk 0 0 0 24000000 0 0 50000 N |
| 202 | sai4 0 0 0 24000000 0 0 50000 N |
| 203 | sai4_root_clk 0 0 0 24000000 0 0 50000 N |
| 204 | sai2 0 0 0 24000000 0 0 50000 N |
| 205 | sai2_root_clk 0 0 0 24000000 0 0 50000 N |
| 206 | sai1 0 0 0 24000000 0 0 50000 N |
| 207 | sai1_root_clk 0 0 0 24000000 0 0 50000 N |
| 208 | lcdif_pixel 0 0 0 24000000 0 0 50000 N |
| 209 | dc_pixel 0 0 0 24000000 0 0 50000 N |
| 210 | disp_dc8000 0 0 0 24000000 0 0 50000 N |
| 211 | disp_root_clk 0 0 0 24000000 0 0 50000 N |
| 212 | disp_dtrc 0 0 0 24000000 0 0 50000 N |
| 213 | noc_apb 1 1 0 24000000 0 0 50000 Y |
| 214 | disp_rtrm 0 0 0 24000000 0 0 50000 N |
| 215 | disp_rtrm_root_clk 0 0 0 24000000 0 0 50000 N |
| 216 | gpu2d_core 0 0 0 24000000 0 0 50000 N |
| 217 | gpu2d_root_clk 0 0 0 24000000 0 0 50000 N |
| 218 | gpu3d_core 0 0 0 24000000 0 0 50000 N |
| 219 | gpu3d_root_clk 0 0 0 24000000 0 0 50000 N |
| 220 | sys_pll3_ref_sel 1 1 0 24000000 0 0 50000 Y |
| 221 | sys_pll3 1 1 0 750000000 0 0 50000 Y |
| 222 | sys_pll3_bypass 1 1 0 750000000 0 0 50000 Y |
| 223 | sys_pll3_out 1 1 0 750000000 0 0 50000 Y |
| 224 | noc 1 1 0 750000000 0 0 50000 Y |
| 225 | arm_pll_ref_sel 1 1 0 24000000 0 0 50000 Y |
| 226 | arm_pll 1 1 0 1200000000 0 0 50000 Y |
| 227 | arm_pll_bypass 1 1 0 1200000000 0 0 50000 Y |
| 228 | arm_pll_out 1 1 0 1200000000 0 0 50000 Y |
| 229 | arm_a53_core 1 1 0 1200000000 0 0 50000 Y |
| 230 | arm 1 1 0 1200000000 0 0 50000 Y |
| 231 | vpu_core 0 0 0 1200000000 0 0 50000 N |
| 232 | vpu_pll_ref_sel 0 1 0 24000000 0 0 50000 Y |
| 233 | vpu_pll 0 1 0 600000000 0 0 50000 Y |
| 234 | vpu_pll_bypass 0 1 0 600000000 0 0 50000 Y |
| 235 | vpu_pll_out 0 2 0 600000000 0 0 50000 N |
| 236 | vpu_g2 0 1 0 600000000 0 0 50000 N |
| 237 | vpu_g2_root_clk 0 1 0 600000000 0 0 50000 N |
| 238 | vpu_g1 0 1 0 600000000 0 0 50000 N |
| 239 | vpu_g1_root_clk 0 1 0 600000000 0 0 50000 N |
| 240 | gpu_pll_ref_sel 0 0 0 24000000 0 0 50000 Y |
| 241 | gpu_pll 0 0 0 800000000 0 0 50000 Y |
| 242 | gpu_pll_bypass 0 0 0 800000000 0 0 50000 Y |
| 243 | gpu_pll_out 0 0 0 800000000 0 0 50000 N |
| 244 | dram_pll_ref_sel 1 1 0 24000000 0 0 50000 Y |
| 245 | dram_pll 1 1 0 750000000 0 0 50000 Y |
| 246 | dram_pll_bypass 1 1 0 750000000 0 0 50000 Y |
| 247 | dram_pll_out 1 1 0 750000000 0 0 50000 Y |
| 248 | dram_core_clk 1 1 0 750000000 0 0 50000 Y |
| 249 | video_pll1_ref_sel 0 0 0 24000000 0 0 50000 Y |
| 250 | video_pll1 0 0 0 594000000 0 0 50000 Y |
| 251 | video_pll1_bypass 0 0 0 594000000 0 0 50000 Y |
| 252 | video_pll1_out 0 0 0 594000000 0 0 50000 N |
| 253 | audio_pll2_ref_sel 0 0 0 24000000 0 0 50000 Y |
| 254 | audio_pll2 0 0 0 650000000 0 0 50000 Y |
| 255 | audio_pll2_bypass 0 0 0 650000000 0 0 50000 Y |
| 256 | audio_pll2_out 0 0 0 650000000 0 0 50000 N |
| 257 | audio_pll1_ref_sel 0 0 0 24000000 0 0 50000 Y |
| 258 | audio_pll1 0 0 0 393216000 0 0 50000 Y |
| 259 | audio_pll1_bypass 0 0 0 393216000 0 0 50000 Y |
| 260 | audio_pll1_out 0 0 0 393216000 0 0 50000 N |
| 261 | sai3 0 0 0 24576000 0 0 50000 N |
| 262 | sai3_root_clk 0 0 0 24576000 0 0 50000 N |
| 263 | clkout2_sel 0 0 0 393216000 0 0 50000 Y |
| 264 | clkout2_div 0 0 0 393216000 0 0 50000 Y |
| 265 | clkout2 0 0 0 393216000 0 0 50000 N |
| 266 | clkout1_sel 0 0 0 393216000 0 0 50000 Y |
| 267 | clkout1_div 0 0 0 393216000 0 0 50000 Y |
| 268 | clkout1 0 0 0 393216000 0 0 50000 N |
| 269 | osc_32k 0 0 0 32768 0 0 50000 Y |
| 270 | root@mesh-10-2:~# |
| 271 | |