Changes between Version 3 and Version 4 of hailoai

Timestamp:

03/20/2024 11:00:00 PM (13 months ago)

Author:

Ryan Erbstoesser

Comment:

add more images

hailoai

@@ -4 +4 @@
 
 They typically come in a M.2 or Mini-PCIe form factor that can be plugged into a Gateworks Single Board Computer (SBC).
+
+'''Please note''' that the Gateworks Venice SBCs have 1x lane of PCIe to each Mini-PCIe slot. Thus any Hailo product that can use 4x lanes will only utilize 1x lane and performance will adjust accordingly.
+
+Note, this page is also related to the following Gateworks Wiki pages:
+ * [wiki:TPU] 
+
+
+[[Image(hailo_hailo8_m2.jpg,300px)]] 
 
 
@@ -89 +97 @@
 
 
-Run HEF File:
+Run HEF File: (pre-compiled HEF (Hailo Executable Format) binary file)
  * Note HEF files can be downloaded here: 
   * [https://github.com/hailo-ai/hailo_model_zoo/blob/master/docs/PUBLIC_MODELS.rst]
@@ -175 +183 @@
             }
           ]
+
+
+== Hailo Tappas
+
+Hailo TAPPAS - Optimized Execution of Video-Processing Pipelines
+TAPPAS is Hailo's set of full application examples, implementing pipeline elements and pre-trained AI tasks.
+
+Read more here [https://github.com/hailo-ai/tappas?tab=readme-ov-file#hailo-tappas---optimized-execution-of-video-processing-pipelines]
         }
       }