Changes between Version 3 and Version 4 of linux/pwm


Ignore:
Timestamp:
06/19/2025 09:25:38 PM (6 days ago)
Author:
Tim Harvey
Comment:

add a venice section

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  • linux/pwm

    v3 v4  
    4141 * The above is an IMX6 showing its 4 controllers available, each controller providing 1 PWM pin. The first one shown (0x208c000 maps to IMX PWM4) is used by the backlight driver. The 2nd (0x2088000 maps to IMX PWM3) is unused. The third one (0x2084000 maps to IMX PWM2) is exported for use by sysfs. The fourth (0x2080000 maps to IMX PWM1) is unused.
    4242
    43 == Ventana PWM mapping ==
    44 The IMX6 SoC has 4 PWM controllers each having a single PWM signal:
     43
     44[=#venice]
     45== Venice PWM
     46The IMX8M SoC's have 4 PWM controllers each having a single PWM output supported in Linux by drivers/pwm/pwm-imx27.c (CONFIG_PWM_IMX27):
     47||= IMX8M controller address =||= pwm =||
     48|| pwm@30660000 || pwm1 ||
     49|| pwm@30670000 || pwm2 ||
     50|| pwm@30680000 || pwm3 ||
     51|| pwm@30690000 || pwm4 ||
     52
     53Only the controllers enabled in the device-tree will be registered and by default current venice boards do not have any dedicated PWM outputs however there are several pins available as other functions that can be pinmuxed to a PWM.
     54
     55The following table shows what PWM's are available on the various Venice baseboard connectors:
     56Venice DIO Mapping:
     57||= Board =||= Connector^^^1^^^ =||= Primary Function^^^2^^^ =||= IMX8M_PAD =||= Default =||= PWM =||= Notes ||
     58|| GW740x  || J14.1 || DIO0 || GPIO1_9 || GPIO1_IO9 || PWM2_OUT ||
     59||         || J14.2 || DIO1 || GPIO1_11 || GPIO1_IO11 || PWM2_OUT ||
     60||         || J14.3 || UART1_RX || UART1_RX || UART1_RX || PWM3_OUT^^^3^^^ || resistor loading option for routing this to GPIO1_14 ||
     61||         || J14.4 || UART1_TX || UART1_TX || UART1_TX || PWM4_OUT^^^3^^^ || resistor loading option for routing this to GPIO1_15 ||
     62||         || J14.5 || I2C4_SCL || I2C4_SCL || I2C4_SCL || PWM2_OUT ||
     63||         || J14.6 || I2C4_SDA || I2C4_SDA || I2C4_SDA || PWM1_OUT ||
     64|| GW730x  || J9.5 / J17.34 || I2C3_SCL || I2C3_SCL   || GPIO5_18 || PWM4_OUT || shared with MIPI connector ||
     65||         || J9.6 / J17.36 || I2C3_SDA || I2C3_SDA   || GPIO5_19 || PWM3_OUT || shared with MIPI connector ||
     66||         || J17.43 || MIPI_GPIO1 || GPIO4_IO04 || GPIO4_IO04 || PWM1_OUT ||
     67|| GW720x  || J9.5 / J17.34 || I2C3_SCL || I2C3_SCL || I2C3_SCL || PWM4_OUT || shared with MIPI connector ||
     68||         || J9.6 / J17.36 || I2C3_SDA || I2C3_SDA || I2C3_SDA || PWM3_OUT || shared with MIPI connector ||
     69||         || J17.43 || MIPI_GPIO1 || GPIO4_IO04 || GPIO4_4 || PWM1_OUT ||
     70|| GW710x  || J4.11 || I2C3_SCL || I2C3_SCL    || GPIO5_18 || PWM4_OUT ||
     71||         || J4.12 || I2C3_SDA || I2C3_SDA    || GPIO5_19 || PWM3_OUT ||
     721. This is the connector pinout.
     732. This is the signal name from the [http://www.gateworks.com/usermanuals ​Venice hardware manuals]
     743. Requires a resistor loading option
     75
     76Note that all signals (unless noted in notes) are 3.3V tolerant.
     77
     78Any of the above pin function assignments can be altered by changing the device-tree to change the pinmux which is also where you can specify drive strength, pull-up, pull-down etc. Read more about gaining more GPIOs via pinmuxing [https://trac.gateworks.com/wiki/linux/devicetree#Venice here]
     79
     80Example:
     81 * GW720x disable I2C3 and enable PWM3/PWM4 (the same changes can be made to the gw73xx.dtsi file)
     82  - device-tree change:
     83{{{#!bash
     84diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72x
     85x.dtsi
     86index 752caa38eb03..417e78ffc0c1 100644
     87--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
     88+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
     89@@ -128,14 +128,6 @@ accelerometer@19 {
     90        };
     91 };
     92 
     93-/* off-board header */
     94-&i2c3 {
     95-       clock-frequency = <400000>;
     96-       pinctrl-names = "default";
     97-       pinctrl-0 = <&pinctrl_i2c3>;
     98-       status = "okay";
     99-};
     100-
     101 &pcie_phy {
     102        fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
     103        fsl,clkreq-unsupported;
     104@@ -191,6 +183,18 @@ eth1: ethernet@0,0 {
     105        };
     106 };
     107 
     108+&pwm3 {
     109+       pinctrl-names = "default";
     110+       pinctrl-0 = <&pinctrl_pwm3>;
     111+       status = "okay";
     112+};
     113+
     114+&pwm4 {
     115+       pinctrl-names = "default";
     116+       pinctrl-0 = <&pinctrl_pwm4>;
     117+       status = "okay";
     118+};
     119+
     120 /* off-board header */
     121 &sai3 {
     122        pinctrl-names = "default";
     123@@ -278,13 +282,6 @@ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4            0x19
     124                >;
     125        };
     126 
     127-       pinctrl_i2c3: i2c3grp {
     128-               fsl,pins = <
     129-                       MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
     130-                       MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
     131-               >;
     132-       };
     133-
     134        pinctrl_pcie0: pcie0grp {
     135                fsl,pins = <
     136                        MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x41
     137@@ -297,6 +294,18 @@ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
     138                >;
     139        };
     140 
     141+       pinctrl_pwm3: pwm3grp {
     142+               fsl,pins = <
     143+                       MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT  0x16
     144+               >;
     145+       };
     146+
     147+       pinctrl_pwm4: pwm4grp {
     148+               fsl,pins = <
     149+                       MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT  0x16
     150+               >;
     151+       };
     152+
     153        pinctrl_reg_usb1_en: regusb1grp {
     154                fsl,pins = <
     155                        MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x41
     156}}}
     157  - userspace:
     158{{{#!bash
     159# ls -l /sys/class/pwm/
     160total 0
     161lrwxrwxrwx 1 root root 0 Jun 19 21:17 pwmchip0 -> ../../devices/platform/soc@0/30400000.bus/30680000.pwm/pwm/pwmchip0
     162lrwxrwxrwx 1 root root 0 Jun 19 21:17 pwmchip1 -> ../../devices/platform/soc@0/30400000.bus/30690000.pwm/pwm/pwmchip1
     163# cat /sys/kernel/debug/pwm
     1640: platform/30680000.pwm, 1 PWM device
     165 pwm-0   ((null)              ): period: 0 ns duty: 0 ns polarity: normal
     166
     1671: platform/30690000.pwm, 1 PWM device
     168 pwm-0   ((null)              ): period: 0 ns duty: 0 ns polarity: normal
     169# echo 0 > /sys/class/pwm/pwmchip0/export # export first PWM (pwm0) on pwmchip0 which is PWM3_OUT because 30680000 is the address of the PWM3 controller)
     170# echo 1000000 > /sys/class/pwm/pwmchip0/pwm0/period # set 1ms period
     171# echo 500000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle # set 500us (50% duty-cycle if period is 1ms)
     172}}}
     173
     174Note that there are 4 PWM controllers but each one has only 1 output thus you only export pwm0
     175
     176[=#ventana]
     177== Ventana PWM
     178The IMX6 SoC has 4 PWM controllers each having a single PWM output supported in Linux by drivers/pwm/pwm-imx27.c (CONFIG_PWM_IMX27):
    45179||= IMX6 controller address =||= IMX6 pwm =||
    46180|| pwm@02080000 || pwm1 ||