Changes between Version 2 and Version 3 of multicoreprocessing

Timestamp:

06/13/2019 09:41:38 PM (5 years ago)

Author:

Cale Collins

Comment:

refactored single core

multicoreprocessing

@@ -188 +188 @@
 = Single Core Processing =
 
-There may be times when a developer needs to only use one CPU because of driver issues, etc. We have found in many instances, especially with wireless application, that they are interrupt intensive and thus the CPU will be running at very low utilization but the interrupt controller is saturated. Since the wireless drivers can only operate on a single core any reduction in overall interrupt traffic helps with performance. When in dual core mode, we use FIQs for inter-processor communication so by running in single core mode we actually reduce the load on the interrupt controller which we’ve seen in some cases provide 5-10% performance improvement. If you are running a lot of user applications then the dual core can definitely provide a benefit it really just depends on your application.  '''NOTE: This mainly applies to the Laguna Family line of ARM11 processors. The ARM9 Ventana has better interrupt capabilities'''
+There may be times when a developer needs to only use one CPU because of driver issues, etc. We have found in many instances, especially with wireless application, that they are interrupt intensive and thus the CPU will be running at very low utilization but the interrupt controller is saturated. Since the wireless drivers can only operate on a single core any reduction in overall interrupt traffic helps with performance. When in dual core mode, we use FIQs for inter-processor communication so by running in single core mode we actually reduce the load on the interrupt controller which we’ve seen in some cases provide 5-10% performance improvement. If you are running a lot of user applications then the dual core can definitely provide a benefit it really just depends on your application.  '''NOTE: This mainly applies to the Laguna Family line of ARM11 processors. Newer processors have better interrupt capabilities'''
 
 To do this, we will modify the bootargs in the bootloader.
 
-For CNS3xxx Laguna boards, break into the bootloader by pressing a key at bootup:
+Break into the bootloader by pressing a key at bootup:
 
 Modify the variable bootargs to include maxcpus=1 at the end of the line as shown below:
 {{{
-Laguna > setenv bootargs console=ttyS0,115200 root=/dev/mtdblock3 rootfstype=squashfs,jffs2 noinitrd init=/etc/preinit maxcpus=1
-}}}
-
-Then save the bootargs with:
-{{{
-Laguna > saveenv
-}}}
+setenv bootargs ${bootargs} maxcpus=1; saveenv
+}}}
+
 
 Note /proc/interrupts at 2 cores: