Changes between Version 1 and Version 2 of newport/PCIe


Ignore:
Timestamp:
02/13/2018 12:10:54 AM (7 years ago)
Author:
Ryan Erbstoesser
Comment:

add link to manuals for pinout.

Legend:

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  • newport/PCIe

    v1 v2  
    2323 - Atomic operations (both 32bit and 64bit CAS, FADD and SWAP)
    2424
     25[=#pinout]
     26== PCIe Pinout ==
     27Please see the user manuals [http://www.gateworks.com/usermanuals here]
     28
    2529[=#throughput]
    26 == PCI Throughput ==
     30== PCIe Throughput ==
    2731The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0Gbits/sec) however this requires a higher co-processor speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 was made because it saves approximately 500mW of power consumption and the lack of Gen3 PCIe card availability.
    2832