| | 39 | |
| | 40 | === Revision D.1 |
| | 41 | Date: 01/13/2018 |
| | 42 | * Add reverse-polarity protection on Vin (see [wiki:newport/errata#np2 Errata NP2]) |
| | 43 | * Add external temperature sensor capable of providing CN80XX CPU die temperature (see [wiki:newport/errata#np3 Errata NP3]) |
| | 44 | * Add CN80XX FUSE blowing capability for chips supporting trusted boot (see [wiki:newport/errata#np4 Errata NP4]) |
| | 45 | * Use 0.22uF AC coupling caps for all PCIe channels as this is required for PCIe gen3 and backward compatible with gen1/2 |
| | 46 | * Improve FAN TACH circuit to support both open drain (OD) and driven TACH outputs |
| | 47 | * Improve MMC trace routing |
| | 48 | * Change boot device from eMMC_SS to the more robust eMMC_LS (which includes an eMMC reset before retry) |
| | 49 | * Add CPU Speed adjustment capability using GSC (requires upcoming GSC feature) |
| | 50 | * Add build option to allow off-board I2C to be at 5V or 3.3V - contact sales@gateworks.com for details |
| | 51 | * Remove unnecessary SATA mux and replace AC coupling caps on PCIe RX differential pair going to J10 miniPCIe socket with 0ohm resistors. If user is going to be using an mSATA device on this socket they may need to have boards built with 0.1uf coupling caps here per the mSATA specification - contact sales@gateworks.com for details - contact sales@gateworks.com for details |
| | 52 | * Add build option to allow isolating J11 miniPCIe clock signals to eliminate contention with non-standard cellular modems - contact sales@gateworks.com for details |
| | 53 | * Add support for optional 802.3bt (PoE++) - contact sales@gateworks.com for details |
