| 342 | |
| 343 | === Revision G |
| 344 | Date: 9/23/2019: |
| 345 | * Replace EOL Wi2Wi GPS receiver with ublox ZOE-M8Q |
| 346 | * Replace EOL 88E1510 RGMII phy (eth0) with DP83867 phy |
| 347 | * Replace EOL ADV7180 with ADV7280A analog video decoder |
| 348 | * Replace EOL HDMI termination with updated version |
| 349 | * Replace EOL 88E8057 MAC/PHY (eth1) with Intel I210 MAC/PHY |
| 350 | * Add GSC input LDO for battery powered applications |
| 351 | * Add full-deplex bridge rectification for eth0/eth1 PoE for full 802.3af compatibility |
| 352 | * Replace input voltage reverse protection diode with Mosfet to improve efficiency at higher input currents |
| 353 | * Add 1K pull-down resistors to the miniPCIe and GbE controller reset outputs |
| 354 | * Add normally-loaded zero ohm resistor on J6 miniPCIe socket clock, TX and RX data pairs to allow isolation for non-compliant cards |
| 355 | * Add normally-loaded zero ohm resistor on all miniPCIe PERST# signals to allow isolation for non-compliant cards |
| 356 | * Add normally enabled power switch to gate 3.3V rail to J6 miniPCIe socket to allow software power control |
| 357 | * Remove un-necessary J9 PCIe RX capacitance |
| 358 | * Replace SATA RX 0.01uF AC coupling capacitor with a 0.1uF device for specification compliance |
| 428 | === Revision G.1 |
| 429 | Date: 9/23/2019: |
| 430 | * Replace EOL Wi2Wi GPS receiver with ublox ZOE-M8Q |
| 431 | * Replace EOL 88E1510 RGMII phy (eth0) with DP83867 phy |
| 432 | * Replace EOL ADV7180 with ADV7280A analog video decoder |
| 433 | * Replace EOL HDMI termination with updated version |
| 434 | * Replace EOL 88E8057 MAC/PHY (eth1) with Intel I210 MAC/PHY |
| 435 | * Add GSC input LDO for battery powered applications |
| 436 | * Add full-deplex bridge rectification for eth0/eth1 PoE for full 802.3af compatibility |
| 437 | * Replace input voltage reverse protection diode with Mosfet to improve efficiency at higher input currents |
| 438 | * Add 1K pull-down resistors to the miniPCIe and GbE controller reset outputs |
| 439 | * Add normally-loaded zero ohm resistor on J7 miniPCIe socket clock, TX and RX data pairs to allow isolation for non-compliant cards |
| 440 | * Add normally-loaded zero ohm resistor on all miniPCIe PERST# signals to allow isolation for non-compliant cards |
| 441 | * Add normally enabled power switch to gate 3.3V rail to J7 miniPCIe socket to allow software power control |
| 442 | * Remove un-necessary J11 PCIe TX capacitance |
| 443 | * Replace SATA RX 0.01uF AC coupling capacitor with a 0.1uF device for specification compliance |