Changes between Version 17 and Version 18 of venice/ethernet
- Timestamp:
- 10/02/2024 11:06:21 PM (7 weeks ago)
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venice/ethernet
v17 v18 6 6 ||= Board =||= Connector =||= Silkscreen =||= U-Boot =||= Linux =||= MAC/Phy =||= Notes =|| 7 7 || GW740x || J21 || Eth!#0 || eth0 || eth0 || IMX8MP EQOS (0x30bf0000) RGMII GPY111 || 802.3at class5 PoE || 8 || || - || - || eth1 || eth1 || IMX8MP FEC (0x30be0000) RGMII KSZ9 477 Port6 || cpu uplink ||8 || || - || - || eth1 || eth1 || IMX8MP FEC (0x30be0000) RGMII KSZ9897STXI/KSZ9477 Port6 || cpu uplink || 9 9 || || J22 || Eth!#1 || lan1 || lan1 || KSZ9477 Port1 || Passive 8-60V PoE || 10 10 || || J22 || Eth!#2 || lan2 || lan2 || KSZ9477 Port2 || || … … 53 53 54 54 Note that from the CPU's perspective 'eth1' is the CPU uplink device 55 to the KSZ9 477 switch so it is never used by itself.55 to the KSZ9897STXI/KSZ9477 switch so it is never used by itself. 56 56 57 57 {{{ … … 103 103 === GW7400 Switch 104 104 105 The GW74xx switched ports utilize a KSZ9 477 switch.105 The GW74xx switched ports utilize a KSZ9897STXI/KSZ9477 switch by Microchip. 106 106 107 107 This is a Distributed Switch Architecture (DSA) setup. Thus, this is not a 'basic hub' that has everything hardwired together.