Venice Ethernet

Venice Ethernet device mapping:

Board	Connector	Silkscreen	U-Boot	Linux	MAC/Phy	Notes
GW740x	J21	Eth#0	eth1	eth1	IMX8MP EQOS RGMII GPY111	802.3at class5 PoE
	-	-	eth0	eth0	IMX8MP FEC RGMII KSZ9477 Port5	cpu uplink
	J22	Eth#1	lan1	lan1	KSZ9477 Port1	Passive 8-60V PoE
	J22	Eth#2	lan2	lan2	KSZ9477 Port2
	J23	Eth#3	lan3	lan3	KSZ9477 Port3
	J23	Eth#4	lan4	lan4	KSZ9477 Port4
	J24	Eth#5	lan5	lan5	KSZ9477 Port5
GW730x	J20	Eth#0	eth0	eth0	IMX8MM FEC RGMII GPY111	802.3at class4 PoE
	J21	Eth#1	eth1	eth1 / enp6s0	PCI LAN7430 or 88E8057	Passive 8-60V PoE
GW720x	J17		eth0	eth0	IMX8MM FEC RGMII GPY111	802.3at class4 PoE
	J17		eth1	eth1 / enp5s0	PCI LAN7430 or 88E8057	Passive 8-60V PoE
GW710x	J16	Ethernet	eth0	eth0	IMX8MM FEC RGMII GPY111	Passive 8-60V PoE

• Port ordering above is from leftmost RJ45 on board when viewing the front-panel
• if 'net.ifnames=0' kernel parameter is specified network interfaces on enumerated busses such as pci/usb are numbered sequentially (ie eth1 instead of enp6s0). See ​Predictable Interface Names for details
• for boards like the GW740x which have a multi-port GbE switch, bandwidth is shared across the downstream ports