Changes between Version 133 and Version 134 of wireless/modem

Timestamp:

10/22/2025 04:49:08 PM (3 days ago)

Author:

Ryan Erbstoesser

Comment:

add notes for pin 20 / 22

wireless/modem

@@ -123 +123 @@
 Most of the Mini-PCIe slots on Gateworks SBCs have PCIe signalling routed to them which can cause conflicts for modems but are required for regular WiFi cards (802.11a/b/g/n/ac). However, there are some slots that do not have PCIe signalling and USB only. Typically these USB only slots are ideal for modems. These exist on some products such as the GW5220, GW6400, among others. Consult the white silkscreen lettering on the PCB board next to the Mini-PCIe slot to see what signalling is routed.
 
-Thus Gateworks typically find pin conflicts (signal mismatch or voltage differences) on the following pins:
+Thus Gateworks typically find pin conflicts (signal mismatch or voltage differences) on the following Mini-PCIe pins:
  * Pin 11 (REFCLK-)
  * Pin 13 (REFCLK+)
@@ -1900 +1900 @@
  * No pinout concerns when using Gateworks GW16140/GW16141 M.2 adapters
   * Note GW16141 requires USB 3.0 which is only available on the i.MX8M Plus and not on the i.MX8M Mini
-  * Pin 20 for enabling PCIe mode is not connected because it is not in the M.2 spec. It is considered a reserved pin, and Gateworks is working to mitigate this in future hardware revisions. 
+  * Pin 20 for enabling PCIe mode is not connected because it is not in the M.2 spec. It is considered a reserved pin, see more info here: [#pin20]
  * Ports: cdc-wdm0 (qmi), ttyUSB0 (unknown), ttyUSB1 (unknown), ttyUSB2 (at), ttyUSB3 (at), ttyUSB4 (unknown), wwan0 (net)
  * Drivers: 
@@ -2429 +2429 @@
 vi /etc/apt/apt.conf.d/20auto-upgrades # set all values to 0
 }}}
+
+[=#pin20]
+= Pin 20 & 22 Details
+
+Pins 20 and 22 are used on some modems for selecting between USB and PCIe mode. 
+
+On the GW16140 M.2 adapter, Pin 22 is not connected, and pin 20 is tied to ground. 
+
+On the GW16FB0-C FSA (used on VeniceFLEX and Catalina), pins 20 and 22 are connected to gpios (M2_GPIO5 and M2_GPIO6 respectively), with more details here: [wiki:FSA#GW16FB0FSAM.2B-KeyAdapter]
+
+On the Venice GW74xx pins 20 and 22 are mapped to GPIO. 
+
+If for some reason the software state of the GPIO is too late during boot (i.e. the modem uses them as power on strapping and you can't control the power-on) then there are resistor loading options on the board (contact support@gateworks.com)
+
+The gpio's can be seen in U-Boot with 'gpio status', are defaulted low and can be manipulated with 'gpio set' and 'gpio clear'. Here is an example showing all the m2 pins:
+{{{
+u-boot=> gpio status
+Bank GPIO1_:
+GPIO1_9: input: 1 [x] dio0.gpio-hog
+GPIO1_11: input: 1 [x] dio1.gpio-hog
+
+Bank GPIO2_:
+GPIO2_6: input: 0 [x] m2_pin20.gpio-hog
+GPIO2_11: input: 0 [x] m2_pin22.gpio-hog
+GPIO2_12: output: 1 [x] tpm_rst#.gpio-hog
+GPIO2_13: output: 1 [x] pcie1_wdis#.gpio-hog
+GPIO2_14: output: 1 [x] pcie3_wdis#.gpio-hog
+GPIO2_15: output: 1 [x] led-0.gpios
+GPIO2_16: output: 0 [x] led-1.gpios
+GPIO2_18: output: 1 [x] pcie2_wdis#.gpio-hog
+
+Bank GPIO3_:
+GPIO3_6: output: 0 [x] m2_rst.gpio-hog
+GPIO3_14: output: 1 [x] m2_wdis2#.gpio-hog
+
+Bank GPIO4_:
+GPIO4_2: output: 1 [x] m2_off#.gpio-hog
+GPIO4_18: output: 1 [x] m2_wdis1#.gpio-hog
+GPIO4_29: output: 1 [x] ethernet@30be0000.phy-reset-gpios
+GPIO4_30: output: 1 [x] ethernet-phy@0.reset-gpios
+GPIO4_31: output: 0 [x] rs485_en.gpio-hog
+
+Bank GPIO5_:
+GPIO5_0: output: 0 [x] rs485_hd.gpio-hog
+GPIO5_1: output: 0 [x] rs485_term.gpio-hog
+GPIO5_14: output: 0 [x] i2c@30a20000.scl-gpios
+GPIO5_15: output: 0 [x] i2c@30a20000.sda-gpios
+GPIO5_16: output: 0 [x] i2c@30a30000.scl-gpios
+GPIO5_17: output: 0 [x] i2c@30a30000.sda-gpios
+u-boot=> gpio set m2_pin20.gpio-hog
+gpio: pin m2_pin20.gpio-hog (gpio 38) value is 1
+u-boot=> gpio set m2_pin22.gpio-hog
+gpio: pin m2_pin22.gpio-hog (gpio 43) value is 1
+
+}}}
+
+
+
+
+
+