wiki:MMC

Version 22 (modified by Tim Harvey, 3 years ago) ( diff )

added bus details

  1. MultiMediaCard (MMC)
    1. Embedded Multi-Media Controller (eMMC)
      1. eMMC bus
      2. eMMC Partitions
      3. eMMC Partition Size Variations
      4. eMMC PARTITION_CONFIG (Boot partition selection)
      5. eMMC Enhanced User Area and Pseudo SLC
      6. U-Boot Support
      7. Linux Support
    2. microSD
      1. MicroSD / uSD Size Limit
      2. MicroSD bus
      3. MicroSD References
    3. Performance and Data Rates
    4. Reliability / Longevity and Program / Erase cycles
    5. Newport
    6. Ventana
    7. Laguna

MultiMediaCard (MMC)

A MultiMediaCard (MMC) is a memory card standard used for solid-state storage typically used in digital cameras, smart-phones, and portable media players. There are several form-factors of cards that fall under the specification. MMC cards use the SDIO data bus standard.

The following Gateworks boards support MMC:

Family Board max clock eMMC2 microSD
Venice GW7400/GW7300/GW7200/GW7100 208MHz 8GB bootable
(~166/40 MB/s read/write HS400) 		SDHC/SDXC DS/HS/UHS-I
~80/40 MB/s read/write SDR1044
GW7401/GW7301/GW7201/GW7101 208MHz 64GB bootable
(~217/76 MB/s read/write HS400) 		SDHC/SDXC DS/HS/UHS-I
~80/40 MB/s read/write SDR1044
Newport GW640x/GW630x/GW620x 35MHz 8GB bootable
(~43/13 MB/s read/write) 		SDHC/SDXC DS/HS bootable3
GW610x 35MHz 8GB bootable
(~43/13 MB/s read/write) 		-
Ventana GW52xx/GW53xx/GW54xx/GW5530 208MHz - SDHC/SDXC DS/HS/UHS-I1 bootable
Laguna GW2388 50MHz - SD/SDHC DS/HS (not bootable)
  1. Earlier Ventana GW52xx/GW53xx/GW54xx board revisions did not support UHS-I - see ventana below
  2. Contact sales@… for other eMMC size options
  3. See newport/#bootdevice for details on booting from the 'alternate boot device'. SD devices (2GB) are not supported.
  4. data rates vary per microSD cards - see spec of card

Performance depends on various factors (see below for more details)

Embedded Multi-Media Controller (eMMC)

Embedded Multi-Media Controller (eMMC) refers to a package consisting of both flash memory and a flash memory controller integrated into a single on-board chip.

eMMC is very similar to a microSD but differs in the following ways:

  • supports several hardware partitions
  • 8-bit data bus
  • Dual-Data-Rate (DDR) (Note this is supported on microSD if the card/controller support UHS-I)
  • device is on-board and thus non removable

eMMC bus

The initial bus speed is started with 25MHz SDR mode and depending on the capabilities of the host and device can negotiate to higher rates:

Mode Data Rate IO voltage Bus width Frequency Max data rate at 8bit bus
Legacy Single 3/1.8/1.2V 1,4,8 0 - 26MHz 26MB/s
High Speed SDR Single 3/1.8/1.2V 1,4,8 0 - 52MHz 52MB/s
High Speed DDR Dual 3/1.8/1.2V 1,4,8 0 - 52MHz 104MB/s
HS400 Single 1.8/1.2V 4,8 0 - 200MHz 200MB/s
HS400 Dual 1.8/1.2V 4,8 0 - 200MHz 400MB/s

eMMC Partitions

eMMC devices are partitioned into several hardware partitions but only one can be selected at a time:

  • BOOT - one or more small partitions intended for boot firmware (eMMC 4.3 spec requires 2 boot and 1 user partition)
  • RPMB - Replay Protected Memory Block - intended to store secure data (ie DRM content protection keys) (eMMC 4.4 spec adds the requirement of an RPMB partition)
  • USER - a large partition intended for general storage

Notes:

  • BOOT and RPMB partitions are configured as SLC while USER can be SLC or MLC.
  • Read / Write commands sent to an eMMC do not directly address the hardware partitions but instead a special command is used to select a partition.
  • A Card Specific Data (CSD) register (EXT_CSD[179]) is used to configure what partition is selected at power-up. This can be configured within Linux via the mmc-utils application, or within U-Boot via the mmc partconf command (see below).
  • It is up to the user to decide if and how to use each of the hardware partitions.

Both Linux (see below) and U-Boot (see below) support accessing the various partitions but in different ways.

eMMC Partition Size Variations

eMMC parts are described as having a single size (ie 4GB, 8GB, 16GB, 32GB, 64GB) but like other block storage devices (rotational hard disks, SSD's, microSD, SD, USB Mass Storage) all vendors parts are not equivalent in the number of 512 Byte blocks (aka sectors) and thus vary in actual size.

Gateworks boards with eMMC FLASH may have a variety of eMMC parts that differ slightly in block size of the boot0/boot1, rpmb, and user partitions. The minimum hardware partition sizes you should count on for Gateworks products are:

eMMC BOOT0/BOOT1 RPMB User Sectors User Size Notes
8GB 4MB 128KB 14876672 7264MB Newport standard
16GB 4MB 128KB 28835840 14080MB option
32GB 4MB 128KB 57671680 28160MB option
64GB 4MB 128KB 119537664 56448MB option

Note in some cases manufacturers may allow you to adjust the Boot and RPMB partition size with a one-time vendor command.

eMMC information available via Linux Userspace:

  • number of blocks in the various partitions reported by /sys/class/block/mmcblk*/size: 
    # size of user partition
printf "%dMiB\n" $((512*$(cat /sys/class/block/mmcblk0/size)/1024/1024))
# size of boot0 partition
printf "%dMiB\n" $((512*$(cat /sys/class/block/mmcblk0boot0/size)/1024/1024))
# size of boot1 partition (will always be the same as boot0)
printf "%dMiB\n" $((512*$(cat /sys/class/block/mmcblk0boot1/size)/1024/1024))
# size of rpmb partition
printf "%dMiB\n" $((512*$(cat /sys/class/block/mmcblk0rpmb/size)/1024/1024))
  • Device name reported by /sys/class/block/mmcblk*/device/name
  • eMMC has CID/OCR/CSD/ECSD registers:
    • CID: 128bits: Card IDentification; found in {/sys/block,/sys/class/block}/mmcblk0/device/name
    • OCR: 32bits: Operation Condition Register; found i n {/sys/block,/sys/class/block}/mmcblk0/device/ocr
    • CSD: 128bits: Card Specific Data; found in {/sys/block,/sys/class/block}/mmcblk0/device/csd
    • ECSD: 512Bytes: Extended Card Specific Data; found in {/sys/class/mmc_host/<hostdev>/csd
  • kernel reports the sizes on detection. For example for a 8GB Micron MTFC8GAKAJCN-4M 
    mmcblk0: mmc0:0001 Q2J55L 7.09 GiB
mmcblk0boot0: mmc0:0001 Q2J55L partition 1 16.0 MiB
mmcblk0boot1: mmc0:0001 Q2J55L partition 2 16.0 MiB
mmcblk0rpmb: mmc0:0001 Q2J55L partition 3 4.00 MiB

Datasheets show the following:

  • Sector Count; SEC_COUNT - number of 512Byte blocks or sectors
  • Boot partition size: BOOT_SIZE_MULT - mult by 128Kb for size of boot0/boot1
  • RPMB size; RPMB_SIZE_MULT - mult by 128Kb for size of rpmb

See also:

eMMC PARTITION_CONFIG (Boot partition selection)

Because eMMC provides multiple hardware partitions but only one can be selected at a time. A non-volatile register in the eMMC device provides a PARTITION_CONFIG that is used to determine what partition is selected at power-up for boot devices. To access this data you need to read/write a 'Card Specific Data' or CSD register (EXT_CSD[179] - EXT_CSC_PART_CONFIG). This can be done both in Linux (see below) or U-Boot (see below).

eMMC Enhanced User Area and Pseudo SLC

The eMMC 4.4 standard introduced the concept of 'Enhanced User Area' in order to improve reliability, performance, and endurance. This allows a one-time configuration of the eMMC to configure all or some of the MLC NAND flash as Psuedo SLC (pSLC) where instead of 2 bits per cell it uses 1 bit per cell. This will reduce the available size of the eMMC as a trade-off for improved reliability, performance, and endurance.

The specification for Enhanced User Area does not specify a particular implementation or require eMMC devices to even support Enhanced User Area.

U-Boot has mmc commands that can be used to configure all or some of an eMMC as enhanced storage.

Example: GW7301:

  • Use 'mmc info' to see current configuration 
    u-boot=> mmc list
FSL_SDHC: 0
FSL_SDHC: 1
FSL_SDHC: 2 (eMMC)
u-boot=> mmc dev 2
switch to partitions #0, OK
mmc2(part 0) is current device
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 13
OEM: 14e
Name: S0J58 
Bus Speed: 52000000
Mode: MMC High Speed (52MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 59.3 GiB
Bus Width: 8-bit
Erase Group Size: 512 KiB
HC WP Group Size: 16 MiB
User Capacity: 59.3 GiB WRREL
Boot Capacity: 31.5 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
    • The above shows that mmc device 2 is an eMMC with:
      • 59.3 GiB capacity in the User hardware partition with write reliability turned on (WRREL). Write reliability is a configuration that affects what happens during an unexpected power-cut; when enabled write operations are atomic and this is typically desired over the higher performance available when this is disabled.
      • 31.5 MiB capacity in the Boot hardware partition configured as enhanced user area (ENH)
      • 4 MiB capacity in the RPMB hardware partition configured as enhanced user area (ENH)
  • use 'mmc hwpartition' to see the current configuration: 
    u-boot=> mmc hwpartition
Partition configuration:
        No enhanced user data area
        No GP1 partition
        No GP2 partition
        No GP3 partition
        No GP4 partition
  • use 'mmc hwpartition user enh' to set enhanced storage with a starting block and a block count (512 byte blocks) which must be aligned with the 'HC WP group size' reported from the 'mmc info' command above. You can use the 'check' option to test the parameters before making it permanent. The 'mmc info' command does not show us the capacity in the number of 512 byte blocks but instead rounds it to GiB or MiB. You can boot to linux and look at /sys/class/block/mmcblk2/size to see the number of 512 byte blocks, which for this particular device is 124321792. 
    u-boot=> mmc hwpartition user enh 0 124321792 check
Partition configuration:
        User Enhanced Start: 0 Bytes
        User Enhanced Size: 59.3 GiB
        No GP1 partition
        No GP2 partition
        No GP3 partition
        No GP4 partition
Total enhanced size exceeds maximum (3794 > 1892)
Failed!
    • This failed due to this eMMC only allowing up to 1892 HC WP Group's. The 'mmc info' command showed us that 'HC WP Group Size' is 16MiB so that means the maximum size we can set to enhanced user area is 1892 * 16MiB = 30272MiB. Devide that by 512bytes gives us 61997056 blocks.
  • use 'mmc hwpartition user enh' again now that we know the max we can request. 
    u-boot=> mmc hwpartition user enh 0 61997056 wrrel on check
Partition configuration:
        User Enhanced Start: 0 Bytes
        User Enhanced Size: 29.6 GiB
        User partition write reliability: on
        No GP1 partition
        No GP2 partition
        No GP3 partition
        No GP4 partition
  • We see no errors now. Once you are satisfied with the offset, size, and capabilities you can add the 'complete' option: 
    u-boot=> mmc hwpartition user enh 0 61997056 wrrel on complete
Partition configuration:
        User Enhanced Start: 0 Bytes
        User Enhanced Size: 29.6 GiB
        User partition write reliability: on
        No GP1 partition
        No GP2 partition
        No GP3 partition
        No GP4 partition
Partitioning successful, power-cycle to make effective
  • After reprogramming eMMC (because we just re-configured the start of the user hardware partition where our boot firmware is) you see the results: 
    u-boot=> mmc dev 2
switch to partitions #0, OK
mmc2(part 0) is current device
u-boot=> mmc info
Device: FSL_SDHC
Manufacturer ID: 13
OEM: 14e
Name: S0J58 
Bus Speed: 52000000
Mode: MMC High Speed (52MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 29.6 GiB
Bus Width: 8-bit
Erase Group Size: 512 KiB
HC WP Group Size: 16 MiB
User Capacity: 29.6 GiB ENH WRREL
User Enhanced Start: 0 Bytes
User Enhanced Size: 29.6 GiB
Boot Capacity: 31.5 MiB ENH
RPMB Capacity: 4 MiB ENH
Boot area 0 is not write protected
Boot area 1 is not write protected
  • Note User hardware partition is now half the size it was before but now is enhanced user area (ENH)

Important notes:

  • changing this is a one-time thing
  • you only get one configuration of offset/size/mode
  • if you change the configuration of your boot area you must re-program the eMMC via JTAG

U-Boot Support

U-Boot provides access to eMMC devices through the mmc command and interface but adds an additional argument to the mmc interface to describe the hardware partition. The interface is therefore described as 'mmc <dev> <part>' where 'dev' is the mmc device (some boards have more than one) and 'part' is the hardware partition: 0=user, 1=boot0, 2=boot1.

Use the mmc dev command to specify the device and partition: 

mmc dev 0 0 # select user hw partition
mmc dev 0 1 # select boot0 hw partition
mmc dev 0 2 # select boot1 hw partition

If U-Boot has been built with CONFIG_SUPPORT_EMMC_BOOT some additional mmc commands are available:

  • mmc bootbus <dev> <boot_bus_width> <reset_boot_bus_width> <boot_mode>
  • mmc bootpart-resize <dev> <boot-part-size-mb> <rpmb-part-size-mb>
  • mmc partconf <dev> <boot_ack> <boot-partition> <partition-access> # set PARTITION_CONFIG field
  • mmc rst-function <dev> <value> # change RST_n_FUNCTION field between 0|1|2 (write-once)

The mmc partconf command can be used to configure the PARTITION_CONFIG specifying what hardware partition to boot from: 

mmc partconf 0 0 0 0 # disable boot partition (default unset condition; boots from user partition)
mmc partconf 0 1 1 0 # set boot0 partition (with ack)
mmc partconf 0 1 2 0 # set boot1 partition (with ack)
mmc partconf 0 1 7 0 # set user partition (with ack)

If U-Boot has been built with CONFIG_SUPPORT_EMMC_RPMB the mmc rpmb command is available for reading, writing and programming the key for the Replay Protection Memory Block (RPMB) partition in eMMC.

When using U-Boot to write to eMMC (or microSD) it is often useful to use the gzwrite command. For example if you have a compressed 'disk image' you can write it to your eMMC (assuming it is mmc dev 0) with: 

tftpboot ${loadaddr} disk-image.gz && gzwrite mmc 0 ${loadaddr} ${filesize}
  • The disk-image.gz contains a partition table at offset 0x0 as well as partitions at their respective offsets (according to the partition table) and has been compressed with gzip
  • If you know the flash offset of a specific partition (which you can determine using the part list mmc 0 command) you can also use gzwrite to flash a compressed partition image

Linux Support

Linux presents the various hardware partitions as separate devices:

  • /dev/mmcblk0boot0 - BOOT0 partition
  • /dev/mmcblk0boot1 - BOOT1 partition
  • /dev/mmcblk0rpmb - RPMB partition
  • /dev/mmcblk0 - USER partition

Note that the BOOT partitions by default are read-only as they are typically used for sensitive boot firmware. To write to them you can disable force_ro in sysfs via: 

echo 0 > /sys/class/block/mmcblk0boot0/force_ro

The Linux mmc application from the mmc-utils package provides access to eMMC configuration through CSD registers.

You can use the mmc utility to configure the eMMC PARTITION_CONFIG to specify the boot device on power-up via mmc bootpart enable <boot_partition> <send_ack> <device> where boot_partition specifies the hardware partition (1=boot0, 2=boot1, 7=user), send_ack specifies the device must send an awknoledgement (for fast boot), and device is the root mmc block device of the eMMC: 

# set boot partition to boot0
mmc bootpart enable 1 0 /dev/mmcblk0
# set boot partition to boot1
mmc bootpart enable 2 0 /dev/mmcblk0
# set boot partition to user
mmc bootpart enable 7 0 /dev/mmcblk0

Some additional use cases: 

# show PARTITION_CONFIG:
mmc extcsd read /dev/mmcblk0 | grep PARTITION_CONFIG
# show BUS CONFIG:
mmc extcsd read /dev/mmcblk0 | grep BOOT_BUS_CONDITIONS
# disable boot partition
mmc bootpart enable 0 0 /dev/mmcblk0

References:

microSD

Gateworks supports microSD (aka uSD) cards on several boards in the Newport, Ventana, and Laguna product families. A microSD card operates at 3.3V (with 3.3V or 1.8V I/O if the board allows it) and uses 4bit I/O. On most Ventana and Newport boards a dual function microSD/SIM connector is used. See the following link for how to load SIM and micoSD cards into this connector. http://trac.gateworks.com/wiki/ventana/simsd

MicroSD / uSD Size Limit

The Ventana, Newport and Venice support SDXC cards which can support up to 2TB.

  • SD 2GB and less
  • SDHC 4GB-32GB
  • SDXC 64GB to 2TB

MicroSD bus

The initial SD bus speed of 12.5MB/s is the default mode defined by SD1.0. Later a 25MB/s High Speed Mode (HS) was defined by SD1.1. As higher performance levels were needed to support new and faster devices the SD association introduced faster bus interfaces: UHS-I, UHS-II, UHS-III, and SD Express. The bus speed is started with 25MHz SDR mode and depending on the capabilities of the host and device can negotiate to higher rates:

Mode Data Rate Max Frequency Max data rate at 8bit bus
Default Speed (DS) Single 25MHz 12.5MB/s
High Speed (HS) Single 50MHz 25MB/s
UHS-I DDR50 Dual 50MHz 50MB/s
UHS-I SDR50 Single 100MHz 50MB/s
UHS-I SDR104 Single 208MHz 104MB/s
  • Note that UHS-I requires support for voltage switching I/O rail from 3.3V to 1.8V
  • All modes start at DS and negotiate up if supported on both host and card

MicroSD References

Performance and Data Rates

Performance of MMC devices depend on the following factors:

  • max clock speed
  • mode: DS/HS/UHS-I
  • bus width: 4-bit for microSD, 8-bit for eMMC
  • cpu performance and DMA capabilities

The SecureDigital (SD) card spec originally defines a speed classes rating to refer to the I/O speed capabilities of the specific card. The class is specified on the card with icons that are denoted in the SD card specification. The class specified the write speed (which was important for Digital cameras) but a shortcoming of this system is it did not specify read speed.

Some examples of speed class rating:

Class Device Write Speed
class2 2MB/sec
class4 4MB/sec
class10 10MB/sec
  • Note: device read speed not specified by class - refer to manufacturer specs

The Ultra High Speed (UHS) bus introduced in version 3 of the SD specification marked by a 'UHS-I' marking on the device supports a higher clock frequency and came with a new rating system that specifies the I/O rate and not the I/O rates supported by the card.

Here are some examples:

Name Clock speed Max possible I/O rate for 4bit MMC SD spec version
DS (Default Speed) 25MHz 12.5 MB/sec 1.01
HS (High Speed) 50MHz 25 MB/sec 2.00
UHS-I SDR12 25MHz 12.5 MB/sec 3.01
UHS-I SDR25 50MHz 25 MB/sec 3.01
UHS-I SDR50 100MHz 50 MB/sec 3.01
UHS-I DDR50 50MHz 50 MB/sec 3.01
UHS-I SDR104 208MHz 104 MB/sec 3.01

SD cards are backwards compatible with respect to clocks: a card capable of UHS-I SDR104 can operate just fine in DS or HS mode.

In any case the actual achievable read/write speeds depend not only on the specified read and write rates by the card vendor but also depend on the microSD Host Controller (uSDHC) of the SoC on the board using the microSD which varies per product family. See below for product family details. References:

Reliability / Longevity and Program / Erase cycles

MMC devices are managed NAND FLASH devices meaning there is a controller inside the part that deals with wear-leveling to move blocks around to avoid over-use of blocks. Parts contain extra blocks such that over time blocks that have to be excluded either because their program/erase cycle max has been reached or blocks fail the devices still retain their original size.

The reliability or longevity of a manged device depends on your use case (rate of program/erase cycles as well as how much of the device is available for use) and the number of extra blocks and therefore varies greatly per device and use case.

Therefore, endurance is expressed in TBW (Terabytes written), which represents the total amount of data that can be written to a storage device during its lifetime of use. A bigger TBW number means longer life.

The value of TBW is inversely proportional to another variable WAF (Write Amplification Factor). WAF is an undesirable phenomenon associated with flash memory, where the actual amount of information physically written to the storage media is a multiple of the logical amount intended to be written.

The WAF of flash memory can be affected by many factors like Garbage collection, Erase, TRIM, wear leveling, sequential writes, random writes.... Therefore, WAF is a variable base on system workload.

For example, workloads of Random Writes will generate a bigger WAF number than workloads of Sequential Writes.

As a simple example here is a calculation for a specific workload on a specific eMMC device:

  • Workload description
    1. 84% Sequential write, 16%Random write
    2. Chunk Size IOs Distribution: 30%: 4KB, 27%: 16KB, 42%: Mix of 8KB, 32KB-256KB, 1%: 512KB
    3. eMMC Cache on
  • specific eMMC device specs (from datasheet):
    • MLC device
    • physical capacity = 0.0037(TB) for 4GB device
    • endurance cycle = 3000 for MLC
  • Write Amplication Factor (WAF):
    • WAF = 4.5 (estimated from the workload description above with simulation)
  • TBW = physical capacity * endurance cycle / WAF
    • TBW = 0.0037(TB) * 3000(cycles) / 4.5(WAF) ~= 2.5 TBW
    • 2.5 Terabytes is the total amount of data written to the device during its lifetime of use, depending on the workload.

For additional detail including Write Amplification Factor for your specific workload you would need to consult the particular storage device manufacturer.

As far as partition block pool isolation goes the boot0/boot1 eMMC partitions share the same block pool for wear-leveling. Therefore if Boot0 is no longer writable because the PE cycles of all boot blocks are over-spec, Boot1 will no longer be writable as well. The User area has its own block pool for wear leveling therefore it would be unaffected by overuse of Boot0/Boot1. While the the User area can be partitioned into an additional 4 Generic Purpose Partitions (GPPs) they still all would use the same block pool assigned to User.

Reference:

Newport

The OCTEON TX CN80XX / CN81XX SoC has a single MMC host controller supporting 3 CMD signals which allows up to three devices to share the bus. Some Newport products support a combination of microSD and on-board eMMC. The MMC host controller supports:

  • 1, 4, 8-bit data bus (8-bit used for eMMC, 4-bit used for microSD)
  • transfer rates up to 52MHz
  • single-data rate (SDR) and dual-data rate (DDR)
  • DMA read/write on 512byte blocks
  • stream mode is not supported but multiblock read/write operations are supported
  • SPI mode not supported
  • BOOT ROM supports booting from MMC

Note that Newport products do not support hot-insert or hot-remove of a microSD. You must have the microSD present at boot in order to use it without running the risk of glitching a transaction to any other device on the shared MMC data bus such as an eMMC. To help enforce this, if a microSD is not present on boot, the BDK will remove it from the Linux device-tree

Newport boards supporting microSD have a connector that supports both SIM and microSD in one.

Ventana

Ventana boards supporting microSD have a connector that supports both SIM and microSD in one. The microSD card offers the following support: Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.

The Freescale IMX6 SoC used on Ventana has an SD host controller that supports up to a 208MHz clock necessary for UHS-I SDR104 however this requires a microSD I/O voltage rail that is switchable between 1.8V and 3.3V which is available only on select Ventana board models (see below). If UHS-I clocking is not available a UHS-I card will be used in HS mode with a 50MHz clock resulting in a theoretical maximum I/O rate of 25MB/sec. Actual raw device throughput (using dd commands) has shown 19.5MB/sec for cards that advertise greater than 20MB I/O when operating in HS mode.

Ventana boards that are capable of UHS-I data rates:

Board model Revision
GW553x A+
GW54xx E+
GW53xx E+
GW520x D+
GW522x B+
  • Standard board models at the revision above will have UHS-I capability loaded by default, however for specials (GW5xx-SPxxx) please contact sales@… to inquire if UHS-I support is available.

From a software perspective, support for UHS-I data rates on UHS-I capable boards is available on:

  • OpenWrt 15.0x BSP based on kernel v4.1 (coming soon)
  • Yocto 1.8 BSP
  • Gateworks downstream vendor kernel v3.14.x

Laguna

The Cavium cns3xxx SoC used on Laguna has an SD host controller that supports:

  • 50MHz clock
  • SD 2.0
  • MMC 4.2

A 4-bit SDR microSD at 50MHz results in a max bus throughput of 25MB/sec (actual results are less as they depend on CPU performance)

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