Changes between Version 20 and Version 21 of PCI


Ignore:
Timestamp:
03/20/2025 06:24:01 PM (11 days ago)
Author:
Tim Harvey
Comment:

clarify venice boards that have gen2 switches

Legend:

Unmodified
Added
Removed
Modified

  • PCI

    v20 v21  
    2323 2. Newport can support PCIe Gen3 via a Gateworks special which modifies a strapping resistor to move the coprocessor clock (SCLK) from 350MHz to 550Mhz (at the cost of ~500mW of power draw).
    2424 3. Venice i.MX 8M has a limitation when the inbound write data transfer size exceeds 400 Bytes, the number of inbound MWr TLP transactions the controller can support is up to the combination of 12 hearders and 400 bytes of data (see [https://comm.eefocus.com/media/download/index/id-1021154 AN13164 iMX8MP PCIe Bandwidth Analysis]. Higher performance can be obtained by having the i.MX 8M Plus issue outbound MRd transactions instead of using inbound MWr.
    25  4. While the IMX8MP supports PCIe Gen3 the GW74xx has a Gen2 switch on it so only supports Gen2
     25 4. While the IMX8MP host supports PCIe Gen3 the GW71xx/GW72xx/GW73xx/GW74xx  have a Gen2 switch on it so only supports Gen2 from host to endpoint
    2626
    2727