Changes between Version 8 and Version 9 of PCI

Timestamp:

06/18/2020 07:23:14 PM (4 years ago)

Author:

Tim Harvey

Comment:

added see also links, table of gateworks board pci capabilities, and throughput section

PCI

@@ -1 +1 @@
 [[PageOutline]]
+
+See also:
+ * [wiki:newport/PCIe]
+ * [wiki:ventana/PCIe]
+
+Gateworks PCI support:
+||= Product Family =||= Capabilities =||
+|| Venice           || PCIe Gen2 ||
+|| Newport          || PCIe Gen2 ^^^2^^^ ||
+|| Ventana          || PCIe Gen1 ^^^1^^^ ||
+ 1. Ventana boards with external clock generators can theoretically support Gen2 however some software modification would be necessary for the PCIe clock configuration.
+ 2. Newport can support PCIe Gen3 via a Gateworks special which modifies a strapping resistor to move the coprocessor clock (SCLK) from 350MHz to 550Mhz (at the cost of ~500mW of power draw).
 
 = PCI 
@@ -49 +61 @@
 Modern generation Gateworks products such as the Laguna GW2391, Ventana, and Newport product families support Mini PCIe cards.
 
+[=#throughput]
+= PCI Throughput
+The PCI specification has evolved to support various generations capable of increasing bus speeds:
+ * PCI Gen3 (8.0GT/sec or 6.4Gbps)
+ * PCI Gen2 (5.0GT/sec or 4Gbps)
+ * PCI Gen1 (2.5GT/sec or 2Gbps)
+
+These are backwards compatible such that a PCI Gen3 link will only be established if the device and host controller support it and otherwise it will step down to Gen2 then Gen1 as needed.
+
+The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.
 
 [=#linux-pci-debug]