Changes between Version 20 and Version 21 of SPI

Timestamp:

04/24/2024 07:25:30 PM (7 months ago)

Author:

Ryan Erbstoesser

Comment:

add venice notes

SPI

@@ -36 +36 @@
 The following Gateworks boards support on-board SPI controllers:
 ||= Family =||= Board =||= Connector =||= Notes =||
+|| Venice  || GW7xxx  || See HW Manual          || single CS^^^2^^^; ecspi2 dts node ||
 || Newport  || GW640x  || J8          || single CS^^^2^^^; spi_7_0 dts node; half-duplex^^^1^^^; modes 1^^^3^^^ ||
 ||          || GW630x  || J8          || single CS^^^2^^^; spi_7_0 dts node; half-duplex^^^1^^^; modes 1^^^3^^^ ||
@@ -50 +51 @@
 See the below product family specific sections for pinout details.
 
+=== Venice
+
+SPI is brought out on most Venice SBCs. Please refer to the hardware manual for pin outs.
+
+Gateworks uses the eCSPI modules of the i.mx8 for external connections. The FlexSPI or QSPI is not used, as this is typically used for flash devices, etc. 
+
+eCSPI{1,2,3} supports data rate up to 52Mbits/s and SPI is a 1bit bus, thus the max bus speed is 52MHz.
+
+Typical pins exposed are:
+- MOSI
+- MISO
+- SCLK (Up to 52MHz clock supported)
+- SS0# (This is chip select 0)
+
 
 === Newport