Changes between Version 21 and Version 22 of SPI

Timestamp:

10/02/2024 07:22:47 PM (7 weeks ago)

Author:

Tim Harvey

Comment:

IMX8M (Venice): added datasheet details about max spi frequency depending on SoC, pins, and direction

SPI

@@ -57 +57 @@
 Gateworks uses the eCSPI modules of the i.mx8 for external connections. The FlexSPI or QSPI is not used, as this is typically used for flash devices, etc. 
 
-eCSPI{1,2,3} supports data rate up to 52Mbits/s and SPI is a 1bit bus, thus the max bus speed is 52MHz.
+While the IMX8MM Datasheet states SPI suports data rates of up to 52Mbits/s the timing details show the following for eCSPI{1,2,3} clock:  
+ * Master mode (Table 30) clk: 23MHz/66Mhz read/write
+ * Slave mode (Table 31) clk: 66Mhz/23MHz read/write
+
+While the IMX8MP Datasheet states SPI suports data rates of up to 52Mbits/s the timing details shows the following for eCSPI{1,2,3} clock:
+ * Master Mode (Table 37)
+|| bus || muxed from || master read (Mhz) || master write (MHz) ||
+|| SPI1 || I2C1/I2C2 || 25 || 50 ||
+|| SPI1 || SPI2      || 30 || 60 ||
+|| SPI2 || SD2       || 30 || 60 ||
+|| SPI2 || SPI2      || 25 || 50 ||
+|| SPI2 || I2C3/I2C4 || 20 || 40 ||
+|| SPI3 || UART1/UART2 || 25 || 50 ||
+ * Slave Mode (Table 38)
+   * 66Mhz/23MHz read/write
 
 Typical pins exposed are:
 - MOSI
 - MISO
-- SCLK (Up to 52MHz clock supported)
-- SS0# (This is chip select 0)
+- SCLK
+- SS0# (This is chip select 0 but note that Linux and U-Boot support any gpio as a chip select)