Changes between Version 23 and Version 24 of SPI

Timestamp:

09/23/2026 10:25:11 PM (44 hours ago)

Author:

Tim Harvey

Comment:

added SPI details for Catalina

SPI

@@ -36 +36 @@
 The following Gateworks boards support on-board SPI controllers:
 ||= Family =||= Board =||= Connector =||= Notes =||
-|| Venice  || GW7xxx  || See HW Manual          || single CS^^^2^^^; ecspi2 dts node ||
+|| Catalina || GW92xx || J22 || SPI4 CS0=TPM, CS1=FSA1, CS2=FSA2, CS3=J22 ||
+|| ||
+|| Venice  || GW82xx  || J7  || SPI2 CS0=TPM, CS1=J7, CS2=FSA1, CS3=FSA2  ||
+||         || GW81xx  ||  || SPI2 CS0=TPM, CS1=FSA1 ||
+||         || GW7xxx  || See HW Manual          || single CS^^^2^^^; ecspi2 dts node ||
 || Newport  || GW640x  || J8          || single CS^^^2^^^; spi_7_0 dts node; half-duplex^^^1^^^; modes 1^^^3^^^ ||
 ||          || GW630x  || J8          || single CS^^^2^^^; spi_7_0 dts node; half-duplex^^^1^^^; modes 1^^^3^^^ ||
@@ -51 +55 @@
 See the below product family specific sections for pinout details.
 
+
+=== Catalina
+SPI is brought out on most Venice SBCs and often shared between multiple devices/connectors each having their own chip-select.
+
+To understand the chip select routing refer to the base-board's device-tree.
+
+The i.MX95 LPSPI interfaces feature:
+ * Up to 30 MHz when operating in master mode.
+ * Operating Modes: Each instance is fully configurable to act as either an SPI Master or SPI Slave.
+ * Word Size: Supports flexible data frame formatting with a configurable word size up to 32-bit.
+ * Data Buffering: Integrated internal FIFO buffers for both transmit and receive channels to minimize data loss.
+ * DMA Integration: Direct support for DMA (Direct Memory Access) transmit and receive requests, allowing background transfers with minimal CPU overhead.
+ * Clock Controls: Fully configurable clock polarity (CPOL) and clock phase (CPHA) settings.
+
 === Venice
 
-SPI is brought out on most Venice SBCs. Please refer to the hardware manual for pin outs.
+SPI is brought out on most Venice SBCs and often shared between multiple devices/connectors each having their own chip-select.
+
+To understand the chip select routing refer to the base-board's device-tree and  refer to the hardware manual for pin outs.
 
 Gateworks uses the eCSPI modules of the i.mx8 for external connections. The FlexSPI or QSPI is not used, as this is typically used for flash devices, etc.