Changes between Version 24 and Version 25 of SPI

Timestamp:

09/23/2026 11:37:19 PM (43 hours ago)

Author:

Ryan Erb

Comment:

add note for catalina

SPI

@@ -68 +68 @@
  * DMA Integration: Direct support for DMA (Direct Memory Access) transmit and receive requests, allowing background transfers with minimal CPU overhead.
  * Clock Controls: Fully configurable clock polarity (CPOL) and clock phase (CPHA) settings.
+
+See Catalina chip select portion of device tree for GW9200 here: [https://github.com/Gateworks/linux-catalina/blob/v6.18.20-catalina/arch/arm64/boot/dts/freescale/imx95-catalina-gw92xx.dtsi#L543] 
 
 === Venice
@@ -147 +149 @@
 }}}
 
+ * Catalina GW9200 (Note TPM is on the first chip select reg=0x0, so user header J22 is reg=0x3, which is chip select 4, but 3 for zero based numbering. spidev3 in the example below is just an example for J22 header) 
+{{{
+&lpspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lpspi4>;
+        cs-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>, /* CS0 TPM */
+                   <&gpio5 14 GPIO_ACTIVE_LOW>, /* CS1 FSA1 */
+                   <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS2 FSA2 */
+                   <&gpio5 12 GPIO_ACTIVE_LOW>; /* CS3 J22 */
+        status = "okay";
+
+        tpm@0 {
+                compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+                reg = <0x0>;
+                spi-max-frequency = <20000000>;
+        };
+        spidev3: spidev@3 {
+                compatible = "rohm,dh2228fv";
+                reg = <0x3>;
+                spi-max-frequency = <20000000>;
+        };
+};
+}}}
+
 
 In the above examples, adjust 'spi-max-frequency' according to the max frequency your slave device can support.