Changes between Version 14 and Version 15 of expansion/gw16168


Ignore:
Timestamp:
07/02/2026 07:08:22 PM (21 hours ago)
Author:
Ryan Erb
Comment:

add pinout

Legend:

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  • expansion/gw16168

    v14 v15  
    2121 * sLLM: small Language Model - a lightweight version of an LLM designed to be more efficient, especially for "edge" devices with limited hardware resources
    2222
    23 == Documentation and links
     23== Documentation and Links
    2424Public:
    2525 * [https://www.nxp.com/design/design-center/software/embedded-software/ara-software-development-kit:ARA-SDK NXP ARA SDK Landing page]
    2626 * https://github.com/nxp-imx/rt-sdk-ara2 - NXP's repo for ara2 runtime SDK v2.04 with dynamic linked binaries
    2727 * https://github.com/nxp-imx-support/uiodma-driver - Kernel driver GPL-2.0
     28
     29= M.2 Pinout
     30
     31The GW16168 follows the very generic and standard M.2 M-Key conventions.
     32
     33 * M2.2,4,12,14,16,18,70,72,74: 3.3VDC
     34 * M2.1,2,9,15,21,27,33,39,45,51,57,71: GND
     35 * M2.6: GND
     36
     37 * M2.40: I2C_SCL 1.8
     38 * M2.42: I2C_SDA 1.8
     39 * M2.50: PCIe_PERST#
     40 * M2.52: P_CLKREQ#
     41 * M2.56: I2C_SDA 3.3
     42 * M2.58: I2C_SCL 3.3
     43
     44 * M2.5: PCIE TXN3
     45 * M2.7: PCIE TXP3
     46 * M2.11: PCIE RXN3
     47 * M2.13: PCIE RXP3
     48
     49 * M2.17: PCIE TXN2
     50 * M2.19: PCIE TXP2
     51 * M2.23: PCIE RXN2
     52 * M2.25: PCIE RXP2
     53
     54 * M2.29: PCIE TXN1
     55 * M2.31: PCIE TXP1
     56 * M2.35: PCIE RXN1
     57 * M2.37: PCIE RXP1
     58
     59 * M2.41: PCIE TXN0
     60 * M2.43: PCIE TXP0
     61 * M2.47: PCIE RXN0
     62 * M2.49: PCIE RXP0
     63
     64 * M2.53: PCIEREFCLKN
     65 * M2.55: PCIEREFCLKP
     66
    2867
    2968