Changes between Version 57 and Version 58 of faq


Ignore:
Timestamp:
04/09/2025 09:58:33 PM (6 days ago)
Author:
Ryan Erbstoesser
Comment:

add faq about more GPIO

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  • faq

    v57 v58  
    352352
    353353Error Correcting Code (ECC) memory is a specific kind of memory designed typically for space applications. Gateworks does not use ECC Memory by default, however, the i.MX8M Plus processor used on some Gateworks SBCs has Inline ECC. Read more from NXP here: [https://www.nxp.com/docs/en/application-note/AN13566.pdf]
     354
     355== How do I get more GPIO / DIO pins?
     356
     357Most of the Gateworks SBCs include 2 to 4 native DIO. If this is not enough for the project, other pins can often be re-allocated to a DIO. This of course means giving up those functions, such as a SPI or I2C bus. This is fairly complex and does require device tree modification, with an example here: [wiki:linux/devicetree#VeniceGW7400GPIODiscussion]