Changes between Version 113 and Version 114 of gsc

Timestamp:

12/19/2023 09:53:16 PM (11 months ago)

Author:

Tim Harvey

Comment:

added venice/malibu GSC R0 factory default setting

gsc

@@ -87 +87 @@
 [=#gsc_ctrl_0]
 === GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
-||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
-|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
-|| 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled||
-|| 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled||
-|| 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled||
-|| 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in [#gsc_firmware_crc GSC_FIRMWARE_CRC (R12-R13)][[BR]] resets to 0 on completion of CRC ||Disabled||Disabled||
-|| 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled||
-|| 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
-|| 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
+||= Bit =||= Name              =||= Description =||
+|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||
+|| 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||
+|| 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||
+|| 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||
+|| 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in [#gsc_firmware_crc GSC_FIRMWARE_CRC (R12-R13)][[BR]] resets to 0 on completion of CRC ||
+|| 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||
+|| 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||
+|| 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) ||
+
+This register typically defaults to the following from the factory:
+ * Malibu / Venice / Ventana: 0x81 (PB_HARD_RESET, CPU_WDOG_POWERCYCLE)
+ * Newport: 0x89 (PB_HARD_RESET, PB_BOOT_ALTERNATIVE, CPU_WDOG_POWERCYLE)
 
 Example: (does not represent defaults or any specific data)