| 793 |  | ||= Bit =||= Name              =||= Description =||  | 
          
            | 794 |  | || 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||  | 
          
            | 795 |  | || 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||  | 
          
            | 796 |  | || 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||  | 
          
            | 797 |  | || 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||  | 
          
            | 798 |  | || 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||  | 
          
            | 799 |  | || 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||  | 
          
            | 800 |  | || 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||  | 
          
            | 801 |  | || 7     ||                     || Reserved ||  | 
          
            |  | 793 | ||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults|| | 
          
            |  | 794 | || 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled|| | 
          
            |  | 795 | || 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled|| | 
          
            |  | 796 | || 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled|| | 
          
            |  | 797 | || 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled|| | 
          
            |  | 798 | || 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||Disabled||Disabled|| | 
          
            |  | 799 | || 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled|| | 
          
            |  | 800 | || 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled|| | 
          
            |  | 801 | || 7     ||                     || Reserved |||||| |