Changes between Version 64 and Version 65 of gsc


Ignore:
Timestamp:
01/05/2021 01:03:56 AM (4 years ago)
Author:
Bobby Jones
Comment:

Large update with v58 release (added some missing v57 documentation as well)

Legend:

Unmodified
Added
Removed
Modified

  • gsc

    v64 v65  
    3636The latest Gateworks products use a third generation GSC. The following generations exist:
    3737||= Family =||= Board =||= GSC version =||
     38|| Venice   || all     || v3 ||
    3839|| Newport  || all     || v3 ||
    3940|| Ventana  || GW5910/GW5913 || v3 ||
    … …  
    5960[=#rtc]
    6061== Real Time Clock ==
    61 The GSC contains a Real Time Clock (RTC) which emulates a Dallas Semiconductor DS1672, or equivalent. The RTC is battery backed to retain time information when SBC power is removed. The I2C address for the RTC is 0x68h. The RTC is compatible with the standard Linux ds1672 RTC driver and thus works with the standard Linux RTC device API documented [http://www.kernel.org/doc/Documentation/rtc.txt here]. The RTC device will be {{{/dev/rtc0}}} and adheres to the standard ioctl and sysfs API's.
     62The GSC contains a Real Time Clock (RTC) which emulates a Dallas Semiconductor DS1672, or equivalent. The RTC is battery backed to retain time information when SBC power is removed. The I2C address for the RTC is {{{0x68}}}. The RTC is compatible with the standard Linux ds1672 RTC driver and thus works with the standard  [http://www.kernel.org/doc/Documentation/rtc.txt Linux RTC device API]. The RTC device will be {{{/dev/rtc0}}} and adheres to the standard ioctl and sysfs API's.
    6263
    6364The most common Linux RTC commands are (refer to the linux man pages for more info on the commands and the available time/date formats):
    … …  
    104105
    105106[=#hwmon_v3]
    106 === GSC v3 (GW6xxx/GW5910/GW5913)
     107=== GSCv3 (GW6xxx/GW5910/GW5913)
    107108The following 16-bit registers (MSB first, LSB second) are available:
    108109
    … …  
    295296The battery voltage rail (vdd_bat) is only able to be measured when the GSC is actually powered off of the battery.
    296297
    297 In some cases you can use the GSC to disable primary board power (referred to as 'GSC Sleep') for a number of seconds in order to refresh the vdd_bat reading. Ventana only requires an off time of 3 seconds in order to read the battery. Newport however requires 35 seconds as it's lower power consumption is not guaranteed to consume the VCC capacitance until that time. In other cases some boards have a GSC_Backup regulator which powers the GSC from Vin even when the GSC has disabled the board's primary power to preserve the GSC battery life and those boards require the board's input power to be fully removed in order to read the GSC battery voltage.
     298In some cases you can use the GSC to disable primary board power (referred to as 'GSC Sleep') for a number of seconds in order to refresh the vdd_bat reading. GSCv2 only requires an off time of 3 seconds in order to read the battery. GSCv3 however requires 35 seconds as it's lower power consumption is not guaranteed to consume the VCC capacitance until that time. In other cases some boards have a GSC_Backup regulator which powers the GSC from Vin even when the GSC has disabled the board's primary power to preserve the GSC battery life and those boards require the board's input power to be fully removed in order to read the GSC battery voltage.
    298299
    299300Boards with a GSC Backup regulator which require board power to be fully removed to re-fresh the GSC battery voltage reading are:
    … …  
    301302 - Ventana GW5224-D+
    302303
    303 When a GSC is running from the GSC battery it re-freshes the battery voltage reading a second or so after it starts running off the battery (ie after board power is removed) as well as every 18 hours.
     304When a GSC is running from the GSC battery it refreshes the battery voltage reading a second or so after it starts running off the battery (ie after board power is removed) as well as every 18 hours.
    304305
    305306
    … …  
    373374[=#gpio]
    374375== General Purpose Input and Output (GPIO) ==
    375 The GSC contains a General Purpose Input and Output (GPIO) port expander which emulates a Texas Instruments PCA9555, or equivalent. The Gateworks board support package maps the PCA9555 GPIO base number to 100 by default (Though this may vary). The functionality supports setting each GPIO signal as an input or output with read-back. For more information on the PCA9555 see the [http://dev.gateworks.com/datasheets/PCA9555.pdf PCA9555 Datasheet]. The I2C address for the PCA9555 is 0x23h.
     376The GSC contains a General Purpose Input and Output (GPIO) port expander which emulates a Texas Instruments PCA9555, or equivalent. The Gateworks board support package maps the PCA9555 GPIO base number to 100 by default (Though this may vary). The functionality supports setting each GPIO signal as an input or output with read-back. For more information on the PCA9555 see the [http://dev.gateworks.com/datasheets/PCA9555.pdf PCA9555 Datasheet]. The I2C address for the PCA9555 is {{{0x23}}}.
    376377
    377378Each board level product has a unique GPIO configuration. Refer to the specific board hardware user manual for more details.
    … …  
    427428== User Pushbutton ==
    428429The GSC offers software controllable user pushbutton configuration. The GSC can be configured to perform a hardware function or raise a host CPU interrupt on certain configurations:
    429  * hardware reset (1x quick press-and-release) - '''default configuration'''
    430  * software interrupt on state change (!r30 firmware and above)
    431  * software interrupt on long (>700ms) press-and-hold
    432  * erase security key EEPROM on 3x quick press-and-release
    433  * reset board and boot from alternate boot device on 5x quick press-and-release (for boards that have an alternate boot device)
     430 * hardware reset (1x quick press and release) - '''default configuration'''
     431 * hardware power down on long (1s) press and hold (configurable with [#GSC_SOFT_POWER_TIME GSC_SOFT_POWER_TIME (R26)] added in GSCv3's v58 firmware)
     432 * software interrupt on state change
     433 * software interrupt on long (>700ms) press and hold
     434 * erase security key EEPROM on 3x quick press and release
     435 * reset board and boot from alternate boot device on 5x quick press-and-release (for boards that have an [#altbootdevice alternate boot device])
    434436 * load default control register values stored in the {{{FACTORY_DEFAULTS}}} section on 10x quick press-and-release (GSCv3, firmware v57 and later)
    435437
    436 The default configuration of the GSC is to perform a hard reset on a quick press-and-release. To change this you need to set the [#gsc_ctrl_0 CTRL_0] register. For example:
     438The default configuration of the GSC is to perform a hard reset on a quick press-and-release. To change this you need to set the [#gsc_ctrl_0 GSC_CTRL_0 (R0)] register. For example:
    437439 * enable all button events
    438440{{{
    … …  
    447449In addition, the user pushbutton state is available on a GPIO in case you need to do anything more flexible than the above built-in interrupt functionality:
    448450||= Family =||= Boards             =||= gsc gpio =||= linux gpio =||
     451|| Venice   || All                  || i2c/0-0023 pca9555 gpio2 || gpio498 ||
     452|| Newport  || All                  || i2c/0-0023 pca9555 gpio2 || gpio450 ||
    449453|| Ventana  || GW5xxx               || i2c/0-0023 pca9555 gpio0 || gpio240 ||
    450454|| Laguna   || GW2380/GW2382/GW2383 || i2c/0-0023 pca9555 gpio8 || gpio108 ||
    … …  
    455459The Linux kernel gpio-keys and gpio-keys-polled (and OpenWrt [wiki:OpenWrt/gpio#button-hotplug-gw gpio-button-hotplug]) drivers can be used to create Linux Input events from GPIO events and interrupt events.
    456460
    457 BSP Specific Notes:
     461
     462
     463'''BSP Specific Notes:'''
    458464 * OpenWrt:
    459465  - the [wiki:OpenWrt/gpio#button-hotplug-gw gpio-button-hotplug] driver is enabled uses the pushbutton GPIO therefore it must be disabled if you want to export it for userspace access. Most likely you can get the functionality you need by using the [=#button-hotplug-gw OpenWrt button-hotplug-gw] package.
    … …  
    475481
    476482
     483
     484
    477485=== Code Examples for software user pushbutton detection ===
    478486The following example will configure the GSC for SW pushbutton interrupt and read the PB state by polling the GPIO (see above):
    … …  
    499507[=#eeprom]
    500508== EEPROM storage ==
    501 The GSC emulates Atmel 24C04 EEPROM storage devices, or equivalent. The EEPROM functionality supports 4Kbits (512bytes) partitioned as shown below. The EEPROM is supported in Linux. The 7-bit I2C base address is 0x50.
     509The GSC emulates Atmel 24C04 EEPROM storage devices, or equivalent. The EEPROM functionality supports 4Kbits (512bytes) partitioned as shown below. The EEPROM is supported in Linux. The 7-bit I2C base address is {{{0x50}}}.
    502510
    503511||= Address    =||= Device Address =||= Size (bytes) =||= Function                  =||
    … …  
    508516|| 0x200-0x2FF  || 0x52: 0x00-0xFF  || 256            || User EEPROM space ^3^       ||
    509517|| 0x300-0x3FF  || 0x53: 0x00-0xFF  || 256            || User EEPROM space ^3^       ||
    510  1. ''Board Info'' EEPROM is reserved for Gateworks
    511   * can be ''write protected'' by enabling EEPROM_WP_BOARDINFO (R15.1)
     518 1. '''Board Info''' EEPROM is reserved for Gateworks
     519  * Can be ''write protected'' by enabling [#gsc_write_protect EEPROM_WP_BOARDINFO (R15.1)]
    512520  * Information about board serialnum, model, manufacturing date, etc can be found in the EEPROM - see [wiki:modelserialnumber here] for details
    513  2. ''Secure Key'' EEPROM is erased if:
    514   * pushbutton is activated 3 times in quick succession (press-and-released <700ms delay between each activation). This function is enabled with R0.1
     521 2. '''Secure Key''' EEPROM is erased if:
     522  * Pushbutton is activated 3 times in quick succession (press-and-released <700ms delay between each activation). This function is enabled with [#gsc_ctrl_0 R0.1]
    515523  * Tamper circuit has been activated (for boards supporting a tamper switch/header)
    516   * The GSC battery is depleted or is removed for more than 10 seconds
    517   * Note that these cases will always erase the ''Secure Key'' EEPROM region regardless of the ''Write Protect'' bits
    518  3. additional 4Kbits (512bytes) available on GW2387/GW2388/GW2391)
    519  4. There are 2 bits in R1 (GSC_CTRL_1) which act as a ''Write Protect'' for EEPROM regions:
    520   * EEPROM_WP_ALL (R15.0) will dissalow user i2c writes to all EEPROM regions (does not affect ''secure key'' erasure cases)
    521   * EEPROM_WP_BOARDINFO (R15.1) will dissallow user i2c writes to the ''Board Info'' EEPROM region
    522  5. The GSC v3 used on the Newport product family provides 128 bytes of '''Secure Key''' area instead of 96.
     524  * The GSC battery is depleted or is removed for more than ~35 seconds
     525  * Note that these cases will always erase the secure key EEPROM region regardless of the ''Write Protect'' bits
     526 3. Additional 4Kbits (512bytes) available on GW2387/GW2388/GW2391)
     527 4. There are 2 bits in [#gsc_ctrl_1 GSC_CTRL_1 (R1)] which act as a ''Write Protect'' for EEPROM regions:
     528  * [#gsc_write_protect EEPROM_WP_ALL (R15.0)] will disallow user i2c writes to all EEPROM regions (does not affect ''secure key'' erasure cases)
     529  * [#gsc_write_protect EEPROM_WP_BOARDINFO (R15.1)] will dissallow user i2c writes to the ''Board Info'' EEPROM region
     530 5. GSCv3 provides 128 bytes of secure key area instead of 96
    523531
    524532GSC firmware update Notes:
    525  * when using {{{gsc_update}}} to update the GSC firmware all user eeprom areas are preserved.
    526  * when using {{{jtag_usbv4}}} to update the GSC firmware via JTAG all user eeprom areas are preserved for GSCv3 (Newport and newer Ventana models)
    527  * when using {{{jtag_usbv4}}} to update the GSC firmware via JTAG all user eeprom areas are erased for GSCv1/GSCv2 (Laguna, Ventana)
     533 * When using {{{gsc_update}}} to update the GSC firmware all user eeprom areas are preserved.
     534 * When using {{{jtag_usbv4}}} to update the GSC firmware via JTAG all user eeprom areas are preserved for GSCv3
     535 * When using {{{jtag_usbv4}}} to update the GSC firmware via JTAG all user eeprom areas are erased for GSCv1/GSCv2
    528536
    529537=== EEPROM Secure Key Example ===
    530 The secure key area starts at 0x51 offset 0x80 and extends for 96 bytes for GSC v1/v2 (!Laguna/Ventana) and for 128 bytes for GSC v2 (Newport).
    531 
    532 To see the secure key, you can use the command i2cdump from the command line: (starts with the ASCII values of D3 and ends with w in below example)
     538The secure key area starts at {{{0x51}}} offset {{{0x80}}} and extends for 96 bytes for GSC v1/v2 and for 128 bytes for GSCv3.
     539
     540To see the secure key, you can use the command {{{i2cdump}}} from the command line: (starts at offset 0x80 and ends with 0xdf in below example)
    533541{{{
    534542#!bash
    … …  
    556564}}}
    557565
    558 To set the bytes from the command line, use a i2cset command. This example shows us writing a 0x3344 of size w (word, 2 bytes) at the beginning of the Secure Key storage at 0x80. The 0x51 is the i2c device address which will remain the same as according to the above information.
     566To set the bytes from the command line, use a {{{i2cset}}} command. This example shows us writing a {{{0x3344}}} of size w (word, 2 bytes) at the beginning of the Secure Key storage at {{{0x80}}}. The {{{0x51}}} is the i2c device address which will remain the same as according to the above information.
    559567{{{
    560568#!bash
    … …  
    569577
    570578=== Custom Serial Number Example ===
    571 For customers who need to add their own serial number, they can write it in the userspace EEPROM space at address 0x50 as shown in the table above.
    572 
    573 Here, a customer specific serial number is created in the userspace EEPROM. For example using the first 6 bytes of userspace EEPROM to store a 6digit serial number in ascii representation:
     579For customers who need to add their own serial number, they can write it in the userspace EEPROM space at address {{{0x50}}} as shown in the table above.
     580
     581Here, a customer specific serial number is created in the userspace EEPROM. For example using the first 6 bytes of userspace EEPROM to store a 6 digit serial number in ASCII representation:
    574582{{{
    575583#!bash
    … …  
    613621[=#powercontrol]
    614622== Hardware Sleep and Wake ==
    615 The GSC has the ability (on the Laguna, Ventana, and Newport product family) has the ability to put the board into a 'Hardware Sleep' mode by disabling the primary power supply. This is very useful in many applications that do not require 24 hour operation and need to save power. In this mode the only item drawing power is the GSC itself (powered by a coin-cell battery). The GSC will 'wake' the board again by enabling the primary power supply when the RTC reaches the time defined in the GSC_SLEEP_WAKE register. The wakeup time can be set to an absolute RTC time by writing to GSC_SLEEP_WAKE or be set relative to the current RTC value by setting the GSC_SLEEP_ADD register and latching it via setting R1.2.
    616 
    617 A pushbutton press will also wake the board unless the SLEEP_NOWAKEPB (R1.3) is enabled.
    618 
    619  * '''NOTE''' : If performing sleep without a coin cell battery, a maximum of 4 seconds should be used for resetting the board. Anything longer may put the board to 'sleep' and not allow it to wake up without pressing the pushbutton or unplugging and plugging in the main power supply.
     623The GSC has the ability to put the board into a 'Hardware Sleep' mode by disabling the primary power supply. This is very useful in many applications that do not require 24 hour operation and need to save power. In this mode the only item drawing power is the GSC itself (powered by a coin-cell battery or similar power source). There are two ways the GSC can engage a board sleep event, via register timers or pushbutton hold.
     624
     625
     626=== Pushbutton Sleep
     627Setting [#gsc_ctrl_0 PB_SOFT_POWER_DOWN R0.2] configures the GSC to do an indefinite hardware sleep if the pushbutton is held for more than 1 second. In order to wake from a sleep started via pushbutton, the pushbutton must be pressed again. This should not be confused with [#gsc_ctrl_0 SWITCH_HOLD R0.6] which will enable a software interrupt when the pushbutton is held for more than 700ms. Both can be set, but typically one is opted for over the other.
     628
     629As of GSCv3 firmware v58, [#GSC_SOFT_POWER_TIME GSC_SOFT_POWER_TIME (R26)] can be used to configure the required press times for both the sleep and wake events. By default the value is {{{0x01}}} which retains the old behavior of 1 second press to sleep and immediate press to wake.
     630
     631An example of setting the wake press time to 4 seconds and the sleep press time to 3 seconds:
     632{{{#!bash
     633# Set R26 to 0x43 for 4 second wake and 3 second sleep times
     634i2cset -f -y 0 0x20 26 0x43
     635}}}
     636
     637=== Register Timer Sleep
     638Registers [#gsc_ctrl_1 GSC_CTRL_1 (R1)] and either [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] or [#gsc_sleep_add GSC_SLEEP_ADD (R6-R9)] can be used to put the board to sleep via i2c. In this situation the GSC will 'wake' the board again by enabling the primary power supply when the RTC reaches the time defined in the [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] registers. The wakeup time can either be set to an absolute RTC time by writing directly to [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] or be set relative to the current RTC value by writing to [#gsc_sleep_add GSC_SLEEP_ADD (R6-R9)] and then latching it by setting [#gsc_ctrl_1 LATCH_SLEEP_ADD (R1.2)]. After [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] has been set using either of the aforementioned methods, setting [#gsc_ctrl_1 ACTIVATE_SLEEP (R1.1)] will put the board to sleep.
     639
     640Once asleep, the GSC will automatically wake the board after the RTC time has reached the [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] value. Alternatively, a pushbutton press will also wake the board unless the [#gsc_ctrl_1 SLEEP_NOWAKEPB (R1.3)] bit is set.
     641
     642 * '''NOTE''' : If performing sleep without a coin cell battery, a maximum of 4 seconds should be used for resetting the board. Anything longer may cause the GSC to lose power and subsequently not allow it to wake up without pressing the pushbutton or power cycling the main power supply.
    620643
    621644==== Board sleeping Example ====
    … …  
    645668}}}
    646669
    647 The board will go to sleep and then wake up after 5 minutes (300secs). If you wanted the board to wakeup at a specific date/time regardless of the current RTC date/time you could set R2-5 to the number of seconds since the epoch (date +%s will show current system time in seconds) instead of using the R6-R9 'relative time' registers.
     670The board will go to sleep and then wake up after 5 minutes (300secs). If you wanted the board to wakeup at a specific date/time regardless of the current RTC date/time you could set [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME (R2-R5)] to the number of seconds since the epoch ({{{date +%s}}} will show current system time in seconds).
    648671
    649672=== GSC Reboot ===
    … …  
    653676[=#altbootdevice]
    654677== Alternate Boot Device ==
    655 Some Gateworks Laguna family products (GW2388) have an ''Alternate boot device'' that can be used for alternate firmware images, such as a flash recovery image. There are 2 ways that you can instruct the GSC to boot to the alternate boot device vs the primary boot device:
    656  1. Press-and-release the user pushbutton 5 times in quick succession (see R0.3 (PB_BOOT_ALTERNATE) below)
    657  2. Use the 'Auto Switch Boot' feature
     678Some Gateworks family products have an ''Alternate boot device'' that can be used for multiple firmware images, such as a flash recovery image. There are a number of ways that you can instruct the GSC to boot to the alternate boot device vs the primary boot device:
     679 1. Press-and-release the user pushbutton 5 times in quick succession (see [#gsc_ctrl_0 PB_BOOT_ALTERNATE (R0.3)])
     680 2. Use the [#AutoSwitchBootDevice Auto Switch Boot] feature
     681 3. Use the [#GSC_BOOT_OPTIONS GSC_BOOT_OPTIONS (R21)] register and power cycle (GSCv3 firmware v57+)
    658682
    659683More details on using the Alternate Boot Device can be found [wiki:gsc/alternate_boot_device here].
    660684
    661685=== Auto Switch Boot Device ===
    662 If the board is equipped with an ''Alternate Boot Device'' you can enable the GSC's ''Auto Switch Boot'' feature by setting R1.6 (SWITCH_BOOT_ENABLE). When a board powers on with this bit set if the 30 second boot watchdog timer expires the GSC will toggle the boot device and power-cycle the board. You can disable the timer for the current boot by setting R1.7 (SWITCH_BOOT_CLEAR) (it will be re-armed on the next power cycle in SWITCH_BOOT_ENABLE has not been cleared).
    663 
    664 For example, if you a supporting firmware updates in your product but want a mechanism to ensure a power loss or other event during a firmware update does not render your device recoverable you can enable this feature and put a 'recovery image' on the alternate boot device.  In this example both firmware images (the primary and the alternate) should set R1.7 within 30 seconds of bootup if that firmware image is desirable.  If either image fails to set R1.7 within the 30 seconds, the board will automatically boot to the other device.
     686If the board is equipped with an alternate boot device such as a micro SD, you can enable the GSC's '''Auto Switch Boot''' feature by setting [#gsc_ctrl_1 SWITCH_BOOT_ENABLE (R1.6)].
     687
     688'''GSCv2''': When a board powers on with this bit set, a 30 second boot watchdog timer begins counting down. If this timer expires before [#gsc_ctrl_1 SWITCH_BOOT_CLEAR (R1.7)] is set, the GSC will toggle the boot device* and power-cycle the board. Most up to date bootloader firmware provided by Gateworks will set this boot check bit automatically, but you can manually disable the timer by setting [#gsc_ctrl_1 SWITCH_BOOT_CLEAR (R1.7)] via i2c. Either way it will be re-armed on the next power cycle unless [#gsc_ctrl_1 SWITCH_BOOT_ENABLE (R1.6)] has been cleared.
     689
     690'''GSCv3 (firmware v57+)''': The boot watchdog is forced on and [#gsc_ctrl_1 SWITCH_BOOT_ENABLE (R1.6)] only controls whether or not the next boot attempt will toggle the boot device.
     691
     692For example, if you a supporting firmware updates in your product but want a mechanism to ensure a failed firmware update does not render your device unrecoverable you can enable this feature and put a 'recovery image' on the alternate boot device. In this example both firmware images (the primary and the alternate) should set [#gsc_ctrl_1 SWITCH_BOOT_CLEAR (R1.7)] within 30 seconds of bootup if that firmware image is desirable.  If either image fails to set this bit within the 30 seconds, the board will automatically power cycle and boot to the other device.
    665693
    666694More details on using the Auto Switch Boot Device can be found [wiki:gsc/alternate_boot_device here].
    … …  
    670698Some boards have a ''Tamper Detect'' circuit implemented either as a physical pushbutton on the board and/or a header that can have an external switch wired to it. The circuit implemented is a ''normally open'' switch to board ground (GND).
    671699
    672 For these boards you can enable the GSC's ''Tamper Detect'' feature by setting bit R0.5 (TAMPER_DETECT) and the accompanying interrupt register bit R11.5 (IRQ_TAMPER_DETECT). Once these bits are set any tamper event produced by a switch closing and the signal conducting to board ground will do the following:
    673  1. set IRQ_TAMPER_DETECT interrupt source bit
    674  2. erase the '''secure key''' EEPROM section
    675  3. produce a GSC interrupt (if board is powered)
     700For these boards you can enable the GSC's ''Tamper Detect'' feature by setting [#gsc_ctrl_0 TAMPER_DETECT (R0.5)] and the accompanying interrupt enable register bit [#gsc_interrupt_enable IRQ_TAMPER_DETECT (R11.5)]. Once these bits are set any tamper event produced by a switch closing and the signal conducting to board ground will do the following:
     701 1. Set [#gsc_interrupt_status IRQ_TAMPER_DETECT (R10.5)] interrupt status bit
     702 2. Erase the '''Secure Key''' EEPROM section
     703 3. Produce a GSC interrupt if board is powered (see [#gsc-interrupts gsc-interrupts])
    676704
    677705* Note: Older revision Ventana models may require a modification for this feature ([wiki:ventana/errata#HW4Tamperswitchnon-functional Errata HW4]), please contact factory at support@gateworks.com
    678706
    679 See also:
    680  [#gsc-interrupts gsc-interrupts]
    681 
    682707[=#activegpsantenna]
    683 == GPS Active Antenna short-circuit auto-detect and recover ==
     708== GPS Active Antenna short-circuit auto detect and recover ==
    684709On some Gateworks products, the Active GPS Antenna has a short-circuit detection circuit that will disable the antenna power if an excessive current draw is detected (ie a short). On some of these products, the GSC will re-enable the antenna power every second in case the short has been removed or replaced. The reason for this protection is two-fold:
    685  1. over-current protection keeps board power available if an antenna short/fault has occurred
    686  2. a shorted/faulty antenna can be replaced without having to power down the board
     710 1. Over-current protection keeps board power available if an antenna short/fault has occurred
     711 2. A shorted/faulty antenna can be replaced without having to power down the board
    687712
    688713Products with GPS antenna protection (GPS is not loaded on all model variants, contact sales@gateworks.com for details):
    … …  
    706731
    707732[=#reset-cause]
    708 == GSC Reset Cause (GSCv3, GSC firmware version v53 or greater)
    709 On most boards, the Gateworks System Controller has the ability to disable primary board power. This is used as a form of 'hard reset' in many cases. You can determine if and why the board was hard reset by looking at the value of the GSC_RESET_CAUSE register.
    710 
    711 Note that the Newport boot firmware will display the reason on bootup. Note that the value of 0, reported as 'VIN' indicates the GSC did not reset the board power supply and the board powered up because of Vin being applied externally.
     733== GSC Reset Cause (GSCv3 firmware v53+)
     734On most boards, the Gateworks System Controller has the ability to disable primary board power. This is used as a form of 'hard reset' in many cases. You can determine if and why the board was hard reset by looking at the value of the [#gsc_reset_cause GSC_RESET_CAUSE (R16)] register.
     735
     736Note that the current Venice and Newport boot firmware will display the reason on bootup. Note that the value of 0, reported as 'VIN' indicates the GSC did not reset the board power supply and the board reset because of Vin being externally cycled.
    712737
    713738Example:
    … …  
    716741i2cget -f -y 0 0x20 16
    717742}}}
    718  The result of this register will be a hex value, consult register table for definition. 
    719 * Boot up of Newport
     743 The result of this register will be a hex value.
     744
     745* Newport boot firmware output
    720746{{{#!bash
    721747Gateworks Newport SPL (dd369f7 Thu Feb 14 22:58:33 UTC 2019)
    … …  
    725751Model   : GW6304-B3
    726752}}}
    727  The value provided in the GSC banner above after "RST:" will be one of the following:
    728  "VIN","PB","WDT","CPU","TEMP_L","TEMP_R","SLEEP","BOOT_WDT1","BOOT_WDT2","SOFT_PWR" consult [#GSC_RESET_CAUSERegisterR16:ResetCause this table]
    729  for definitions.   
     753
     754 The value provided in the GSC banner above after "RST:" will be a short ASCII string.
     755
     756Consult the associated [#gsc_reset_cause register table] for numerical value and ASCII flag string definitions.
    730757
    731758[=#thermal-protection]
    732 == GSC Thermal Protection (GSCv3, GSC firmware version v53 or greater)
     759== GSC Thermal Protection (GSCv3 firmware v53+)
    733760The Gateworks System Controller has the ability to monitor board temperature and CPU temperature and disable board primary power when either of those exceeds specified values.
    734761
    735 If either the GSC 'board temperature' exceeds 85C or the 'external thermal sensor' exceeds its threshold (100C for Newport CPU Junction Temperature (Tj)) the GSC will disable the primary power supply for a 'cooldown period'. The cooldown period has a minimum of 5 seconds, a maximum of 300 seconds, and will increase by 30 seconds each time a thermal threshold event occurs. If no thermal threshold event occurs within 300 seconds of power-up the cooldown period will be reset to the minimum of 5 seconds.
     762If either the GSC 'board temperature' exceeds {{{85C}}} or the 'external thermal sensor' exceeds its threshold ({{{100C}}} for Newport CPU Junction Temperature (Tj)) the GSC will disable the primary power supply for a 'cooldown period'. The cooldown period has a range of {{{5-300}}} seconds, and will increase from {{{5}}} by {{{30}}} seconds each time a thermal threshold event occurs. If no thermal threshold event occurs within {{{300}}} seconds of power-up the cooldown period will be reset to the minimum of {{{5}}} seconds.
    736763
    737764This feature is present on:
    … …  
    741768 - GW6400-B+
    742769
    743 Thermal protection is controlled by the GSC_THERMAL_PROTECT register R19.
    744 
    745 **Note:** Thermal protection is enabled automatically by the Gateworks boot firmware.  This is indicated by "Thermal Protection Enabled" as seen in the SPL output below:
     770Thermal protection is controlled by [#gsc_thermal_protect GSC_THERMAL_PROTECT (R19)].
     771
     772**Note:** Thermal protection is enabled automatically by current Gateworks boot firmware.  This is indicated by "Thermal Protection Enabled" as seen in the SPL output below:
    746773{{{#!bash
    747774GSC     : v53 0x0e68 RST:VIN Thermal Protection Enabled
    … …  
    750777[=#gsc-interrupts]
    751778== GSC Interrupts
    752 The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The GSC_INTERRUPT_ENABLE register defines what events can trigger an interrupt and an interrupt service routine can query the GSC_INTERRUPT_STATUS register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the GSC_INTERRUPT_STATUS register.
    753 
    754 See also:
    755  * [#gsc_interrupt_status GSC_INTERRUPT_STATUS register]
    756  * [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE register]
     779The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0 (R11)] register defines what events can trigger an interrupt and an interrupt service routine can query the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register.
     780
     781'''GSCv3''' has an additional pair of interrupt registers represented by [#GSC_INTERRUPT_SOURCE_1 GSC_INTERRUPT_STATUS_1 (R17)] and [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1 (R18)].
    757782
    758783[=#IRQ_PB]
    759784=== IRQ_PB interrupt ===
    760 The IRQ_PB interrupt occurs if the user pushbutton has been pressed then released within 700ms thus signifying a quick 'press-and-release' event. Note that the PB_HARD_RESET bit must be cleared in the GSC_CTRL_0 register for this to occur otherwise a pushbutton will cause a hard board reset.
     785The IRQ_PB interrupt occurs if the user pushbutton has been pressed then released within 700ms thus signifying a quick 'press-and-release' event. Note that the PB_HARD_RESET bit must be cleared in the [#gsc_ctrl_0 GSC_CTRL_0 (R0)] register for this to occur otherwise a pushbutton will cause a hard board reset.
    761786
    762787See also:
    … …  
    765790[=#IRQ_SWITCH_HOLD]
    766791=== IRQ_SWITCH_HOLD interrupt ===
    767 The IRQ_SWITCH_HOLD interrupt occurs if SWITCH_HOLD is enabled in the GSC_CTRL_0 register and the user pushbutton was held for over 1 second.
     792The IRQ_SWITCH_HOLD interrupt occurs if SWITCH_HOLD is enabled in the [#gsc_ctrl_0 GSC_CTRL_0 (R0)] register and the user pushbutton was held for over 1 second.
    768793
    769794See also:
    … …  
    772797[=#IRQ_SECURE_KEY_ERASED]
    773798=== IRQ_SECURE_KEY_ERASED interrupt ===
    774 The IRQ_SECURE_KEY_ERASED interrupt occurs after the user key EEPROM area has been erased. This can occur because of either a tamper event (see TAMPER_DETECT) or because 3x quick button press-and-release events have occurred (see PB_CLEAR_SECURE_KEY).
     799The IRQ_SECURE_KEY_ERASED interrupt occurs after the user key EEPROM area has been erased. This can occur because of either a tamper event (see [#gsc_ctrl_0 TAMPER_DETECT (R0.5)]) or because 3x quick button press-and-release events have occurred (see [#gsc_ctrl_0 PB_CLEAR_SECURE_KEY (R0.1)]).
    775800
    776801See also:
    … …  
    780805[=#IRQ_EEPROM_WP]
    781806=== IRQ_EEPROM_WP interrupt ===
    782 The IRQ_EEPROM_WP interrupt occurs if the GSC_EEPROM_WP_ALL or GSC_EEPROM_BOARDINFO bits are set in the GSC_WRITE_PROTECT register and a write protect violation has occurred.
     807The IRQ_EEPROM_WP interrupt occurs if the {{{GSC_EEPROM_WP_ALL}}} or {{{GSC_EEPROM_BOARDINFO}}} bits are set in the [#gsc_write_protect GSC_WRITE_PROTECT (R15)] register and a write protect violation has occurred.
    783808
    784809See also:
    … …  
    787812[=#IRQ_GPIO_CHANGE]
    788813=== IRQ_GPIO_CHANGE interrupt ===
    789 The IRQ_GPIO_CHANGE interrupt occurs if a GSC GPIO which is configured as an input has changed state. Note that the GSC GPIO controller emulates a PCA9555 chip.
     814The [#gsc_interrupt_status IRQ_GPIO_CHANGE] interrupt occurs if a GSC GPIO which is configured as an input has changed state. Note that the GSC GPIO controller emulates a PCA9555 chip.
    790815
    791816Note that this interrupt needs to be enabled if you wish to sense user pushbutton press and release events independently (for example, you are trying to implement your own timing, or using the Linux {{{gpio-keys}}} driver which creates Linux input events from GPIO based buttons).
    792817
    793 Note that some boards route one or more GSC based GPIO's to various off-board connectors for use as general purpose digital I/O (DIO) or tamper switch circuits. As such, these ports are configured as inputs by default and if unconnected (un-terminated electrically) can cause spurious IRQ_GPIO_CHANGE interrupt events when enabled.
     818Note that some boards route one or more GSC based GPIO's to various off-board connectors for use as general purpose digital I/O (DIO) or tamper switch circuits. As such, these ports are configured as inputs by default and if unconnected (un-terminated electrically) can cause spurious [#gsc_interrupt_status IRQ_GPIO_CHANGE] interrupt events when enabled.
    794819
    795820To avoid this make sure you configure unused inputs as outputs. Note that the GSC will not allow a dedicated input GPIO to be set as an output so there is no harm in just defaulting all to outputs as long as there are no GPIO's connected to off-board circuits that will cause undesirable affects if drive high or low.
    … …  
    807832[=#IRQ_TAMPER_DETECT]
    808833=== IRQ_TAMPER_DETECT interrupt ===
    809 The IRQ_TAMPER_DETECT interrupt occurs if TAMPER_DETECT has been enabled in the GSC_CTRL_0 register and the tamper circuit is broken. Only certain products have one or more tamper circuits. If supported the tamper signals are connected to a normally closed to ground button.
     834The [#gsc_interrupt_status IRQ_TAMPER_DETECT] interrupt occurs if {{{TAMPER_DETECT}}} has been enabled in the [#gsc_ctrl_0 GSC_CTRL_0 (R0)] register and the tamper circuit is broken. Only certain products have one or more tamper circuits. If supported the tamper signals are connected to a normally closed to ground button.
    810835
    811836See also:
    … …  
    814839[=#IRQ_WDOG_TIMEOUT]
    815840=== IRQ_WDOG_TIMEOUT interrupt ===
    816 The IRQ_WDOG_TIMEOUT interrupt indicates that the GSC boot watchdog caused a board level power cycle and as such can't be caught via software (as the board was power cycled) but can be detected at power-on as the reason for reset.
     841The [#gsc_interrupt_status IRQ_WDOG_TIMEOUT] interrupt indicates that the GSC boot watchdog caused a board level power cycle and as such can't be caught via software (as the board was power cycled) but can be detected at power-on as the reason for reset.
    817842
    818843Note that the Ventana bootloader reads and clears this status register but displays the result.
    … …  
    821846[=#watchdog]
    822847== Hardware Boot Watchdog ==
    823 Gateworks boards benefit from a GSC Boot Watchdog which will cause a primary board power supply reset if the bootloader fails to load and disable it within 30 seconds. This protects against occasional chip errata that our hardware has no control over.
     848Gateworks boards benefit from a GSC Boot Watchdog which will cause a primary board power supply reset if the bootloader fails to load and disable it within {{{30}}} seconds. This protects against occasional chip errata that our hardware has no control over.
    824849
    825850
    826851[=#registers]
    827852== GSC Registers
    828 The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of 0x20.
     853The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of {{{0x20}}}.
    829854
    830855GSC Registers:
    … …  
    927952[=#gsc_write_protect]
    928953=== GSC_WRITE_PROTECT (Register R15): Write Protection
    929 ||= Bit =||= Name =||= Description                                                                                      =||
    930 || 0     || GSC_EEPROM_WP_ALL       || 1 = Write Protect all EEPROM regions                                              ||
     954||= Bit =||= Name =||= Description =||
     955|| 0     || GSC_EEPROM_WP_ALL || 1 = Write Protect all EEPROM regions ||
    931956|| 1     || GSC_EEPROM_WP_BOARDINFO || 1 = Write Protect the reserved Gateworks '''Board Info''' EEPROM section          ||
    932 || 2     ||                         || Reserved                                                                          ||
    933 || 3-7   || GSC_WP_PASSWD           || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
     957|| 2     || Reserved || - ||
     958|| 3-7   || GSC_WP_PASSWD || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
    934959
    935960[=#gsc_reset_cause]
    936961=== GSC_RESET_CAUSE (Register R16): Reset Cause
    937 Supported on GSCv3, the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC.
    938 
    939 ||= Value =||= Name =||= Description =||
    940 || 0  || RST_CAUSE_VIN             || Board power was applied - normal powerup; no reset ||
    941 || 1  || RST_CAUSE_PB              || User pushbutton ||
    942 || 2  || reserved                  || reserved ||
    943 || 3  || RST_CAUSE_CPU             || CPU watchdog ||
    944 || 4  || RST_CAUSE_TEMP_LOCAL      || Board Temperature exceeded spec ||
    945 || 5  || RST_CAUSE_TEMP_REMOTE     || CPU Temperature exceeded spec ||
    946 || 6  || RST_CAUSE_SLEEP           || GSC woke board from sleep ||
    947 || 7  || RST_CAUSE_BOOT_WDT        || Boot watchdog ||
    948 || 8  || RST_CAUSE_BOOT_WDT_MANUAL || User pushbutton 5x to toggle boot device ||
    949 || 9  || RST_CAUSE_SOFT_PWR        || Button press from soft power control ||
     962Supported on '''GSCv3 firmware v53+''', the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC. This register is read by up to date Newport and Venice boot firmware and displays an ASCII flag representation. See the [#reset-cause reset cause] section for more detail.
     963
     964||= Value =||= Name =||= ASCII Flag =||= Description =||
     965|| 0  || RST_CAUSE_VIN             || VIN || Board power was cycled externally; no reset ||
     966|| 1  || RST_CAUSE_PB              || PB || User pushbutton ||
     967|| 2  || Reserved                  || - || - ||
     968|| 3  || RST_CAUSE_CPU             || CPU || CPU watchdog ||
     969|| 4  || RST_CAUSE_TEMP_LOCAL      || TEMP_L || Board Temperature exceeded spec ||
     970|| 5  || RST_CAUSE_TEMP_REMOTE     || TEMP_R || CPU Temperature exceeded spec ||
     971|| 6  || RST_CAUSE_SLEEP           || SLEEP || GSC woke board from sleep ||
     972|| 7  || RST_CAUSE_BOOT_WDT        || BOOT_WDT1 || Boot watchdog ||
     973|| 8  || RST_CAUSE_BOOT_WDT_MANUAL || BOOT_WDT2 || User pushbutton 5x to toggle boot device ||
     974|| 9  || RST_CAUSE_SOFT_PWR        || SOFT_PWR || Button press from soft power control ||
    950975
    951976
    … …  
    966991[=#gsc_thermal_protect]
    967992=== GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
    968 Supported on GSCv3 (v53: 20181107 and later firmware), the GSC_THERMAL_PROTECT register configures the thermal protection feature.
     993Supported on '''GSCv3 firmware v53+''', the GSC_THERMAL_PROTECT register configures the thermal protection feature.
    969994
    970995||= Bit =||= Name =||= Description =||
    … …  
    10551080[[CollapsibleEnd]]
    10561081
     1082[=#GSC_CTRL_2]
     1083=== GSC_CTRL_2 (Register R23): Pushbutton, Miscellaneous Configuration
     1084Supported in '''GSCv3 firmware v58+'''.
     1085
     1086||= Value =||= Name =||= Description =||
     1087|| 0 || GSC_10X_PRESS_DISABLE || Disable 10x press for loading FACTORY registers (see [#GSC_REGISTER_BACKUP register backup]) ||
     1088|| 1 || GSC_SOFT_WAKE_PROTECT || Disable waking from soft power press if VIN below board preset minimum ||
     1089
     1090[=#GSC_SOFT_POWER_TIME]
     1091=== GSC_SOFT_POWER_TIME (Register R26): Soft Power Press Time
     1092Supported in '''GSCv3 firmware v58+'''. This register controls how long (in seconds) the pushbutton must be depressed before the board turns on/off via soft power control. The register is composed of an upper and lower nibble that control the minimum power on and power off press times respectively. The register defaults to a power on press time of {{{0}}} seconds and a power off press time of {{{1}}} second ({{{0x01}}}).
     1093
     1094||= Value =||= Name =||= Description =||
     1095|| 0-3 || GSC_SOFT_POWER_TIME_ON || Minimum pushbutton press time required to wake, in seconds ||
     1096|| 4-7 || GSC_SOFT_POWER_TIME_OFF || Minimum pushbutton press time required to sleep, in seconds ||
     1097
    10571098[=#GSC_REGISTER_BACKUP]
    10581099=== GSC_REGISTER_BACKUP (Register R31): Register Backup Control
    … …  
    10661107
    10671108[=#reg_save_load]
    1068 == Register !Save/Load (GSCv3, firmware version v57 or later)
     1109== Register !Save/Load (GSCv3 firmware v57+)
    10691110With the release of GSCv3 firmware version v57 the GSC now has the ability to save and load the control register set. The registers affected are all registers available from the {{{0x20}}} chip address, with the exception of non control registers such as the status, CRC, and firmware version registers.
    10701111
    10711112The register saves are stored in a non volatile section of memory, allowing them to persist across power loss events. When the the GSC resets for whatever reason, it will first attempt to load the register values from the {{{USER_DEFAULTS}}} section if values previously saved by the user exist. Otherwise the {{{FACTORY_DEFAULTS}}} values will be loaded instead.
    10721113
    1073 There are currently two places registers are saved, a non user accessible {{{FACTORY_DEFAULTS}}} section that is populated with the factory programmed register values, and a {{{USER_DEFAULTS}}} section that contains the current control register values when the user executes a {{{GSC_REG_BKP_SAVE}}} command via register [#GSC_REGISTER_BACKUP R31] described above. From the same [#GSC_REGISTER_BACKUP R31], a user can remotely load register defaults from either location. As an additional recovery measure, a {{{10x}}} press of the pushbutton will load the values stored in the {{{FACTORY_DEFAULTS}}} location and reset the GSC as well as powercycle the board.
    1074 
    1075 == Code Examples
    1076 
    1077 The following examples show how to utilize some of the GSC features and functions.
    1078 
    1079 * Reading the GSC Registers
    1080  * Use {{{i2cget}}} to read the GSC registers
    1081   * {{{i2cget -f -y BUS# DEVICE-ADDRESS# REGISTER#}}}
    1082   * For example, to read register 14:
    1083    * {{{i2cget -f -y 0 0x20 14}}}
    1084    * For the GSC, always use 0 and 0x20 for the BUS and DEVICE
    1085 
    1086 * Board sleeping for 10 seconds
    1087  * The following example will sleep the board for 10 seconds by setting the “add timer” to 10 seconds (from the current time) and then putting the board to sleep. This example uses the Linux I2C utilities.
    1088 {{{
    1089 #!bash
    1090 i2cset -f -y 0 0x20 6 10        ;# write add timer to 10sec
    1091 i2cset -f -y 0 0x20 7 0
    1092 i2cset -f -y 0 0x20 8 0
    1093 i2cset -f -y 0 0x20 9 0
    1094 i2cset -f -y 0 0x20 1 0x4       ;# set add time bit
    1095 i2cset -f -y 0 0x20 1 0x3       ;# enable (put board to sleep)
    1096 }}}
    1097 
    1098 The board will go to sleep and then wake up after 10 seconds. If you wanted the board to wakeup at a specific date/time regardless of the current RTC date/time you could set R2-5 to the number of seconds since the epoch ({{{date +%s}}} will show current system time in seconds) instead of using the R6-R9 'relative time' registers but note that if you set a value that has already passed you will have to activate the boards user pushbutton (if present) or remove the GSC battery for 10 seconds to reset the GSC/RTC to be able to wakeup the board.
    1099 
    1100 * Reading GSC version
    1101  * The following example will print out the GSC code revision. This example uses the Linux I2C utilities.
    1102 {{{
    1103 i2cget -f -y 0 0x20 14          ;# read GSC revision from register 14
    1104 0x16                            ;# hex revision value = v22
    1105 }}}
     1114There are currently two places registers are saved, a non user accessible {{{FACTORY_DEFAULTS}}} section that is populated with the factory programmed register values, and a {{{USER_DEFAULTS}}} section that contains the current control register values when the user executes a {{{GSC_REG_BKP_SAVE}}} command via register [#GSC_REGISTER_BACKUP GSC_REGISTER_BACKUP (R31)] described above. From this register, a user can remotely load register defaults from either location. As an additional recovery measure, a {{{10x}}} press of the pushbutton will load the values stored in the {{{FACTORY_DEFAULTS}}} location and reset the GSC as well as powercycle the board.
     1115
    11061116
    11071117[=#i2c]
    … …  
    11091119The GSC communicates with the SoC via i2c at a maximum clock rate of 100KHz.
    11101120
    1111 The v1 and v2 GSC (see [#versions above]) may occasionally be busy and fail to ACK an i2c master transaction within the bit timing. The v3 GSC used in the Newport and newer product families is not susceptible to this.
     1121GSC v1 and v2 (see [#versions above]) may occasionally be busy and fail to ACK an i2c master transaction within the bit timing. The GSCv3 used in the Newport and newer product families is not susceptible to this.
     1122
     1123Reading the GSC registers example using {{{i2cget}}}:
     1124{{{#!bash
     1125# i2cget -f -y <BUS> <DEVICE-ADDRESS> <REGISTER>
     1126# For the GSC, always use 0 and 0x20 for the BUS and DEVICE
     1127# Read the GSC version from R14:
     1128i2cget -f -y 0 0x20 14
     1129}}}
    11121130
    11131131[=#nak]
    1114 === Occasional I2C NAK's ===
    1115 I2C NAK's can occur on v1 and v2 GSC's. This is because every second the GSC performs a round of ADC conversions for its hardware monitoring function. At worst, you should never fail an ACK more than 2 times in a row based on the amount of time needed for the ADC conversions.
     1132== Occasional I2C NAK's ==
     1133I2C NAK's can occur on GSC v1 and v2. This is because every second the GSC performs a round of ADC conversions for its hardware monitoring function. At worst, you should never fail an ACK more than 2 times in a row based on the amount of time needed for the ADC conversions.
    11161134
    11171135For this reason, you should retry and i2c read/write calls up to 3 times if the failure is a NAK (failure to ACK).
    … …  
    11601178Device-tree bindings for the KEYBOARD_GPIO (gpio-keys) driver are used to map the user pushbutton gpio as well as the other GSC status interrupt events to Linux input events.
    11611179
    1162 These actions depend on the manual user configuration of the [#gsc_ctrl_0 GSC CTRL_0] register. The driver does 'not' force a configuration upon the user. Note that all Gateworks boards ship with  pushbutton configured as a hard-reset (R0.0=1) and that this register is non-volatile as long as the GSC battery is powering the GSC. In such a default configuration a quick press/release of the user pushbutton will result in a hard reset instead of an interrupt that can be caught by software.
     1180These actions depend on the manual user configuration of the [#gsc_ctrl_0 GSC_CTRL_0 (R0)] register. The driver does 'not' force a configuration upon the user. Note that all Gateworks boards ship with  pushbutton configured as a hard-reset (R0.0=1) and that this register is non-volatile as long as the GSC battery is powering the GSC. In such a default configuration a quick press/release of the user pushbutton will result in a hard reset instead of an interrupt that can be caught by software.
    11631181
    11641182The following table shows what linux input EV_KEY event is sent for each event:
    … …  
    11701188|| 5           || BTN_4 || tamper event                                            || R0.5=1 (tamper detect enabled)                           || ||
    11711189|| 7           || BTN_5 || user button held >700ms                                 || R0.6=1 (switch hold enabled)                             || event fires 700ms after press ||
    1172  * In addition to the requirements for GSC_CTRL_0 listed above, the associated bit in R11 corresponding to the interrupt number also must be enabled.
    1173 
    1174 The driver does not alter the configuration of CTRL_0 so the user must do so manually depending on their interests. Some example configurations are:
     1190 * In addition to the requirements for [#gsc_ctrl_0 GSC_CTRL_0 (R0)] listed above, the associated bit in [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0 (R11)] corresponding to the interrupt number also must be enabled.
     1191
     1192The driver does not alter the configuration of [#gsc_ctrl_0 GSC_CTRL_0 (R0)] so the user must do so manually depending on their interests. Some example configurations are:
    11751193 * enable all events (allows catching individual button press and button release events):
    11761194{{{