Changes between Version 65 and Version 66 of gsc

Timestamp:

01/05/2021 01:08:54 AM (4 years ago)

Author:

Bobby Jones

Comment:

Shift gsc registers to top of page

gsc

@@ -56 +56 @@
   - reduced power consumption resulting in longer battery life (3.8Y -> 5Y)
   - resolves 'high power draw state' when inserting a battery while board powered off
+
+
+[=#registers]
+== GSC Registers
+The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of {{{0x20}}}.
+
+GSC Registers:
+||= Reg Number =||= Reg Name           =||= Description                                 =||= Supported =||
+|| 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         || All ||
+|| 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device || All ||
+|| 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            || All ||
+|| 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   || All ||
+|| 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              || All ||
+|| 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              || All ||
+|| 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            || All ||
+|| 14           || GSC_FIRMWARE_VER     || Firmware Version                              || All ||
+|| 15           || GSC_WRITE_PROTECT    || Write Protection                              || All ||
+|| 16           || GSC_RESET_CAUSE      || Reset Cause                                   || GSCv3 ||
+|| 17           || GSC_INTERRUPT_SOURCE_1 || Interrupt Source 1                          || GSCv3 ||
+|| 18           || GSC_INTERRUPT_ENABLE_1 || Interrupt Enable 1                          || GSCv3 ||
+|| 19           || GSC_THERMAL_PROTECT  || Thermal Protection                            || GSCv3 ||
+|| 20           || GSC_CPU_SPEED_CTRL   || CPU Speed Control                             || GSCv3 ||
+|| 21           || GSC_BOOT_OPTIONS     || Boot Control Options                          || GSCv3 ||
+|| 22           || GSC_MEM_ACCESS_PAGE  || Direct Memory Access Page Number              || GSCv3 ||
+|| 23           || GSC_CTRL_2           || Pushbutton Switch, Misc.                      || GSCv3 ||
+|| 31           || GSC_REGISTER_BACKUP  || Thermal Protection                            || GSCv3 ||
+
+[=#gsc_ctrl_0]
+=== GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
+||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
+|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
+|| 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled||
+|| 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled||
+|| 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled||
+|| 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||Disabled||Disabled||
+|| 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled||
+|| 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
+|| 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
+
+[=#gsc_ctrl_1]
+=== GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control
+||= Bit =||= Name              =||= Description =||
+|| 0     || SLEEP_ENABLE        || 0 = Disable hardware sleep operation[[BR]] 1 = Enable hardware sleep operation ||
+|| 1     || ACTIVATE_SLEEP      || 0 = Do not activate hardware sleep operation[[BR]] 1 = Activate hardware sleep operation (see GSC_SLEEP_WAKE) ||
+|| 2     || LATCH_SLEEP_ADD     || 0 = Reserved[[BR]] 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE[[BR]]Resets to Zero on Completion ||
+|| 3     || SLEEP_NOWAKEPB      || 0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time ||
+|| 4     || RESERVED            || ||
+|| 5     || RESERVED            || ||
+|| 6     || SWITCH_BOOT_ENABLE  || 0 = Auto Switch boot disabled[[BR]] 1 = Auto Switch boot enabled[[BR]]Note this is set and used at powerup by the GSC as a '''boot watchdog''' on Ventana boards ||
+|| 7     || SWITCH_BOOT_CLEAR   || Auto Switch boot clear[[BR]]Set to disable auto switch boot countdown timer[[BR]]Note this is set and used at bootup by the bootloader as a '''boot watchdog''' on Ventana boards ||
+
+[=#gsc_sleep_wake_time]
+=== GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time
+||= Bit =||= Description =||
+|| 0-31  || RTC Value to wake the board when in sleep[[BR]] (least significant byte first) ||
+
+[=#gsc_sleep_add]
+=== GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive
+||= Bit =||= Description =||
+|| 0-31  || Add to current RTC and store in GSC_SLEEP_WAKE_TIME[[BR]] latched with R1.2[[BR]] (least significant byte first) ||
+
+[=#gsc_interrupt_status]
+=== GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
+The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
+
+||= Bit =||= Name =||= Description =||
+|| 0     || IRQ_PB            || When set a pushbutton switch interrupt has occurred ||
+|| 1     || IRQ_KEY_ERASED    || When set a '''Secure Key''' erase operation has completed ||
+|| 2     || IRQ_EEPROM_WP     || When set an EEPROM WP violation occurred[[BR]] (write to EEPROM while GSC_EEPROM_WP_ALL or GSC_EEPROM_WP_BOARDINFO was enabled) ||
+|| 3     ||                   || Reserved ||
+|| 4     || IRQ_GPIO_CHANGE   || When set a GPIO interrupt has occurred ||
+|| 5     || IRQ_TAMPER_DETECT || When set a tamper switch interrupt has occurred ||
+|| 6     || IRQ_WDOG_TIMEOUT  || When set a boot watchdog timeout has occurred resulting in the board being reset ||
+|| 7     || IRQ_SWITCH_HOLD   || When set a 'switch hold' interrupt has occurred ||
+
+For more information see [#gsc-interrupts gsc-interrupts]
+
+[=#gsc_interrupt_enable]
+=== GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)
+||= Bit =||= Name =||= Description =||
+|| 0     || IRQ_PB                || Set to enable pushbutton switch interrupt ||
+|| 1     || IRQ_SECURE_KEY_ERASED || Set to enable '''Secure Key''' erase operation interrupt ||
+|| 2     || IRQ_EEPROM_WP         || Set to enable EEPROM WP violation interrupt ||
+|| 3     ||                       || Reserved ||
+|| 4     || IRQ_GPIO_CHANGE       || Set to enable GPIO interrupt ||
+|| 5     || IRQ_TAMPER_DETECT     || Set to enable Tamper detect interrupt ||
+|| 6     || IRQ_WDOG_TIMEOUT      || Set to enable Boot Watchdog timeout interrupt ||
+|| 7     || IRQ_SWITCH_HOLD       || Set to enable pushbutton switch 'hold' interrupt ||
+
+For more information see [#gsc-interrupts gsc-interrupts]
+
+[=#gsc_firmware_crc]
+=== GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value
+||= Bit  =||= Description =||
+||  0-15  || Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first)[[BR]] The GSC performs a CRC check when R0.4 is set[[BR]] Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC. ||
+
+
+[=#gsc_firmware_ver]
+=== GSC_FIRMWARE_VER (Register R14): GSC Firmware Version
+||= Bit =||= Description                            =||
+|| 0-7   || Contains the GSC firmware version number ||
+
+
+[=#gsc_write_protect]
+=== GSC_WRITE_PROTECT (Register R15): Write Protection
+||= Bit =||= Name =||= Description =||
+|| 0     || GSC_EEPROM_WP_ALL || 1 = Write Protect all EEPROM regions ||
+|| 1     || GSC_EEPROM_WP_BOARDINFO || 1 = Write Protect the reserved Gateworks '''Board Info''' EEPROM section          ||
+|| 2     || Reserved || - ||
+|| 3-7   || GSC_WP_PASSWD || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
+
+[=#gsc_reset_cause]
+=== GSC_RESET_CAUSE (Register R16): Reset Cause
+Supported on '''GSCv3 firmware v53+''', the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC. This register is read by up to date Newport and Venice boot firmware and displays an ASCII flag representation. See the [#reset-cause reset cause] section for more detail.
+
+||= Value =||= Name =||= ASCII Flag =||= Description =||
+|| 0  || RST_CAUSE_VIN             || VIN || Board power was cycled externally; no reset ||
+|| 1  || RST_CAUSE_PB              || PB || User pushbutton ||
+|| 2  || Reserved                  || - || - ||
+|| 3  || RST_CAUSE_CPU             || CPU || CPU watchdog ||
+|| 4  || RST_CAUSE_TEMP_LOCAL      || TEMP_L || Board Temperature exceeded spec ||
+|| 5  || RST_CAUSE_TEMP_REMOTE     || TEMP_R || CPU Temperature exceeded spec ||
+|| 6  || RST_CAUSE_SLEEP           || SLEEP || GSC woke board from sleep ||
+|| 7  || RST_CAUSE_BOOT_WDT        || BOOT_WDT1 || Boot watchdog ||
+|| 8  || RST_CAUSE_BOOT_WDT_MANUAL || BOOT_WDT2 || User pushbutton 5x to toggle boot device ||
+|| 9  || RST_CAUSE_SOFT_PWR        || SOFT_PWR || Button press from soft power control ||
+
+
+[=#GSC_INTERRUPT_SOURCE_1]
+=== GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
+
+||= Value =||= Name =||= Description =||
+|| 0 || GSP_IRQ_OVRTMP_LOCAL || When set the local temp rose above CRIT_BOARD_TEMP ||
+|| 1 || GSP_IRQ_OVRTMP_REMOTE || When set the remote temp sensor asserted its ALERTJ signal ||
+
+[=#GSC_INTERRUPT_ENABLE_1]
+=== GSC_INTERRUPT_ENABLE_1 (Register R18): Interrupt Enable 1
+
+||= Value =||= Name =||= Description =||
+|| 0 || GSP_IRQ_OVRTMP_LOCAL || Set to enable the local temp rose above CRIT_BOARD_TEMP interrupt ||
+|| 1 || GSP_IRQ_OVRTMP_REMOTE || Set to enable the remote temp sensor asserted ALERTJ signal interrupt ||
+
+[=#gsc_thermal_protect]
+=== GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
+Supported on '''GSCv3 firmware v53+''', the GSC_THERMAL_PROTECT register configures the thermal protection feature.
+
+||= Bit =||= Name =||= Description =||
+|| 0     || GSC_TP_ENABLE || 1 = Enable Thermal protection ||                                     
+
+[=#GSC_BOOT_OPTIONS]
+=== GSC_BOOT_OPTIONS (Register R21): Boot Control Options
+
+||= Value =||= Name =||= Description =||
+|| 0 || GSC_SWITCH_BOOT_SELECT || Boot device select. Clear for primary, set for alt device. This bit is also controlled by the [#UserPushbutton user pushbutton] 5x press behavior.  ||
+
+[=#GSC_MEM_ACCESS_PAGE]
+=== GSC_MEM_ACCESS_PAGE (Register R22): Direct Memory Access Page Number
+
+||= Value =||= Name =||= Description =||
+|| 0-7 || GSC_PAGE_NUMBER || Page address offset when direct reading the GSC flash ||
+
+This API which is implemented over I2C on address {{{0x5f}}} allows a user to do direct memory reads over the entirety of the accessible memory range ({{{0x0000-0xFFFF}}}). It is used by constructing a 16 bit address with the top byte (a.k.a. page) being set by writing to an undocumented register at address {{{0x20}}} offset {{{0x1f}}}. The bottom byte is then added on via standard I2C protocol. Memory writes are not supported with this API. In order to simplify the usage of this API, a bash script was created that will be posted on the wiki and/or given to FAE's to distribute as they see fit. The name of the script is {{{gsc_direct_mem.sh}}} and the contents are included below. 
+
+ [[CollapsibleStart(GSC Direct Memory Read Script)]]
+{{{#!bash
+#!/bin/bash
+
+[ "$#" -ne 2 ] && {
+        echo "This script acts as a wrapper around I2C commands in order to do direct memory reads of the GSC."
+        echo "It will output the i2c response in an i2cdump type format."
+        echo
+        echo "Usage: $0 <offset> <length>"
+        echo
+        echo "Example usage to read all 2000(0x7d0) peripheral register values:"
+        echo "  $0 0x100 0x7d0"
+        exit 1
+}
+
+# Store inputs
+BUS=0
+ADDR=0x5e
+OFFSET=$1
+LENGTH=$2
+
+# Misc variables
+COUNT=0
+PAGE=0
+PRINTVAL=0x0000
+REMAINDER=0
+HIGH=
+RETURN=
+
+# Calculate initial page number based on passed in offset
+PAGE=$((OFFSET / 0x100))
+OFFSET=$((OFFSET % 0x100))
+
+echo "      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f     0123456789abcdef"
+while [[ $COUNT -ne $LENGTH ]]; do
+        # Set the page number accordingly
+        i2cset -f -y 0 0x20 0x16 $PAGE
+
+        # Do either a full i2cdump or specify a range if bytes aren't a 0x100 aligned block
+        if [[ $(($LENGTH - $COUNT)) -lt 0x100 || $OFFSET -ne 0 ]]; then
+                HIGH=$(($LENGTH - $COUNT - 1 + $OFFSET))
+                # Record remainder for i2c 0x100 upper range limit
+                if [[ $HIGH -gt 0x100 ]]; then
+                        REMAINDER=$(($HIGH + 1 - 0x100))
+                else
+                        REMAINDER=0
+                fi
+
+                RETURN=$(i2cdump -f -y -r ${OFFSET}-$(($HIGH - $REMAINDER)) 0 $ADDR b | grep ':')
+                COUNT=$(($HIGH - $REMAINDER - $OFFSET + 1 + $COUNT))
+                OFFSET=0
+        else
+                RETURN=$(i2cdump -f -y 0 $ADDR b | grep ':')
+                COUNT=$(($COUNT + 0x100))
+        fi
+
+        if [[ "$RETURN" ]]; then # Only print reads
+                # Format output to be continuous and account for page increase
+                echo "$RETURN" | while read x; do
+                        printf "%04x" "$((0x$(echo $x | cut -d':' -f1) + $((PAGE * 0x100))))"
+                        echo ":${x##*:}"
+                done
+        fi
+
+        # Increase the page count
+        ((++PAGE))
+done
+}}}
+[[CollapsibleEnd]]
+
+[=#GSC_CTRL_2]
+=== GSC_CTRL_2 (Register R23): Pushbutton, Miscellaneous Configuration
+Supported in '''GSCv3 firmware v58+'''. 
+
+||= Value =||= Name =||= Description =||
+|| 0 || GSC_10X_PRESS_DISABLE || Disable 10x press for loading FACTORY registers (see [#GSC_REGISTER_BACKUP register backup]) ||
+|| 1 || GSC_SOFT_WAKE_PROTECT || Disable waking from soft power press if VIN below board preset minimum ||
+
+[=#GSC_SOFT_POWER_TIME]
+=== GSC_SOFT_POWER_TIME (Register R26): Soft Power Press Time
+Supported in '''GSCv3 firmware v58+'''. This register controls how long (in seconds) the pushbutton must be depressed before the board turns on/off via soft power control. The register is composed of an upper and lower nibble that control the minimum power on and power off press times respectively. The register defaults to a power on press time of {{{0}}} seconds and a power off press time of {{{1}}} second ({{{0x01}}}).
+
+||= Value =||= Name =||= Description =||
+|| 0-3 || GSC_SOFT_POWER_TIME_ON || Minimum pushbutton press time required to wake, in seconds ||
+|| 4-7 || GSC_SOFT_POWER_TIME_OFF || Minimum pushbutton press time required to sleep, in seconds ||
+
+[=#GSC_REGISTER_BACKUP]
+=== GSC_REGISTER_BACKUP (Register R31): Register Backup Control
+This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information.
+
+||= Value =||= Name =||= Description =||
+|| 1 || GSC_REG_BKP_SAVE || Save current register values to USER backup area ||
+|| 2 || GSC_REG_BKP_USER_LOAD || Load register values from USER backup ||
+|| 3 || GSC_REG_BKP_FACTORY_LOAD || Load register values from FACTORY backup ||
+|| 4-7 || GSC_REG_BKP_PASSWORD || Password for upper nibble ({{{0xA0}}}). Bitwise OR this value with lower nibble enumerated values described above ||
 
 
@@ -847 +1105 @@
 == Hardware Boot Watchdog ==
 Gateworks boards benefit from a GSC Boot Watchdog which will cause a primary board power supply reset if the bootloader fails to load and disable it within {{{30}}} seconds. This protects against occasional chip errata that our hardware has no control over.
-
-
-[=#registers]
-== GSC Registers
-The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of {{{0x20}}}.
-
-GSC Registers:
-||= Reg Number =||= Reg Name           =||= Description                                 =||= Supported =||
-|| 0            || GSC_CTRL_0           || Pushbutton Switch, CRC, Tamper Switch         || All ||
-|| 1            || GSC_CTRL_1           || Sleep / Wakeup Control, Alternate Boot Device || All ||
-|| 2-5          || GSC_SLEEP_WAKE_TIME  || Sleep Wakeup Timer                            || All ||
-|| 6-9          || GSC_SLEEP_ADD        || Sleep Wakeup Additive Timer                   || All ||
-|| 10           || GSC_INTERRUPT_SOURCE || Interrupt Source                              || All ||
-|| 11           || GSC_INTERRUPT_ENABLE || Interrupt Enable                              || All ||
-|| 12-13        || GSC_FIRMWARE_CRC     || Firmware CRC Value                            || All ||
-|| 14           || GSC_FIRMWARE_VER     || Firmware Version                              || All ||
-|| 15           || GSC_WRITE_PROTECT    || Write Protection                              || All ||
-|| 16           || GSC_RESET_CAUSE      || Reset Cause                                   || GSCv3 ||
-|| 17           || GSC_INTERRUPT_SOURCE_1 || Interrupt Source 1                          || GSCv3 ||
-|| 18           || GSC_INTERRUPT_ENABLE_1 || Interrupt Enable 1                          || GSCv3 ||
-|| 19           || GSC_THERMAL_PROTECT  || Thermal Protection                            || GSCv3 ||
-|| 20           || GSC_CPU_SPEED_CTRL   || CPU Speed Control                             || GSCv3 ||
-|| 21           || GSC_BOOT_OPTIONS     || Boot Control Options                          || GSCv3 ||
-|| 22           || GSC_MEM_ACCESS_PAGE  || Direct Memory Access Page Number              || GSCv3 ||
-|| 23           || GSC_CTRL_2           || Pushbutton Switch, Misc.                      || GSCv3 ||
-|| 31           || GSC_REGISTER_BACKUP  || Thermal Protection                            || GSCv3 ||
-
-[=#gsc_ctrl_0]
-=== GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration
-||= Bit =||= Name              =||= Description =||=Newport Defaults=||=Ventana Defaults||
-|| 0     || PB_HARD_RESET       || 0 = Pushbutton Software Interrupt[[BR]] Generates GSC Interrupt (see R10.0/R11.0)[[BR]] 1 = Push button generates hard system reset to board when the button is[[BR]] activated and de-activated within 700ms ||Enabled||Enabled||
-|| 1     || PB_CLEAR_SECURE_KEY || 0 = Clear '''Secure Key''' EEPROM disabled[[BR]] 1 = Clear GSC EEPROM user space when switch is activated three times with[[BR]] less than 700ms delay between each activation[[BR]] Generates GSC Intterupt ||Disabled||Disabled||
-|| 2     || PB_SOFT_POWER_DOWN  || 0 = Soft Power Down disabled[[BR]] 1 = Soft Power Down enabled[[BR]]Hold down >1s to power down[[BR]]When powered down a momentary press will power up[[BR]] Generates push button interrupt ||Disabled||Disabled||
-|| 3     || PB_BOOT_ALTERNATE   || 0 = Boot Alternate Device disabled.[[BR]] 1 = Boot Alternate Device Enabled[[BR]] The board will reset and boot from the Alternate Boot Device when the[[BR]] pushbutton is activated (quick press-and-release) 5 times in quick succession) ||Enabled||Disabled||
-|| 4     || PERFORM_CRC         || 1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13)[[BR]] resets to 0 on completion of CRC ||Disabled||Disabled||
-|| 5     || TAMPER_DETECT       || 0 = Do not activate tamper switch operation[[BR]] 1 = Activate tamper switch operation. When Activated, if the tamper switch[[BR]] is released, the contents in the EEPROM user space will be erased[[BR]] Generates tamper switch interrupt. ||Disabled||Disabled||
-|| 6     || SWITCH_HOLD         || 0 = Switch hold disabled.[[BR]] 1 = Switch Hold On. When the switch is held down for >700ms an interrupt[[BR]] will be generated. See interrupt Enable / Status registers. (supported in rev29+) ||Disabled||Disabled||
-|| 7     || CPU_WDOG_POWERCYCLE || 0 = Disabled. CPU WDOG signals only trigger a software reset. [[BR]] 1 = Enabled. Convert CPU WDOG signal into a full board power cycle. (GSCv3 only) || Enabled || Not supported ||
-
-[=#gsc_ctrl_1]
-=== GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control
-||= Bit =||= Name              =||= Description =||
-|| 0     || SLEEP_ENABLE        || 0 = Disable hardware sleep operation[[BR]] 1 = Enable hardware sleep operation ||
-|| 1     || ACTIVATE_SLEEP      || 0 = Do not activate hardware sleep operation[[BR]] 1 = Activate hardware sleep operation (see GSC_SLEEP_WAKE) ||
-|| 2     || LATCH_SLEEP_ADD     || 0 = Reserved[[BR]] 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE[[BR]]Resets to Zero on Completion ||
-|| 3     || SLEEP_NOWAKEPB      || 0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time ||
-|| 4     || RESERVED            || ||
-|| 5     || RESERVED            || ||
-|| 6     || SWITCH_BOOT_ENABLE  || 0 = Auto Switch boot disabled[[BR]] 1 = Auto Switch boot enabled[[BR]]Note this is set and used at powerup by the GSC as a '''boot watchdog''' on Ventana boards ||
-|| 7     || SWITCH_BOOT_CLEAR   || Auto Switch boot clear[[BR]]Set to disable auto switch boot countdown timer[[BR]]Note this is set and used at bootup by the bootloader as a '''boot watchdog''' on Ventana boards ||
-
-[=#gsc_sleep_wake_time]
-=== GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time
-||= Bit =||= Description =||
-|| 0-31  || RTC Value to wake the board when in sleep[[BR]] (least significant byte first) ||
-
-[=#gsc_sleep_add]
-=== GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive
-||= Bit =||= Description =||
-|| 0-31  || Add to current RTC and store in GSC_SLEEP_WAKE_TIME[[BR]] latched with R1.2[[BR]] (least significant byte first) ||
-
-[=#gsc_interrupt_status]
-=== GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
-The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
-
-||= Bit =||= Name =||= Description =||
-|| 0     || IRQ_PB            || When set a pushbutton switch interrupt has occurred ||
-|| 1     || IRQ_KEY_ERASED    || When set a '''Secure Key''' erase operation has completed ||
-|| 2     || IRQ_EEPROM_WP     || When set an EEPROM WP violation occurred[[BR]] (write to EEPROM while GSC_EEPROM_WP_ALL or GSC_EEPROM_WP_BOARDINFO was enabled) ||
-|| 3     ||                   || Reserved ||
-|| 4     || IRQ_GPIO_CHANGE   || When set a GPIO interrupt has occurred ||
-|| 5     || IRQ_TAMPER_DETECT || When set a tamper switch interrupt has occurred ||
-|| 6     || IRQ_WDOG_TIMEOUT  || When set a boot watchdog timeout has occurred resulting in the board being reset ||
-|| 7     || IRQ_SWITCH_HOLD   || When set a 'switch hold' interrupt has occurred ||
-
-For more information see [#gsc-interrupts gsc-interrupts]
-
-[=#gsc_interrupt_enable]
-=== GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)
-||= Bit =||= Name =||= Description =||
-|| 0     || IRQ_PB                || Set to enable pushbutton switch interrupt ||
-|| 1     || IRQ_SECURE_KEY_ERASED || Set to enable '''Secure Key''' erase operation interrupt ||
-|| 2     || IRQ_EEPROM_WP         || Set to enable EEPROM WP violation interrupt ||
-|| 3     ||                       || Reserved ||
-|| 4     || IRQ_GPIO_CHANGE       || Set to enable GPIO interrupt ||
-|| 5     || IRQ_TAMPER_DETECT     || Set to enable Tamper detect interrupt ||
-|| 6     || IRQ_WDOG_TIMEOUT      || Set to enable Boot Watchdog timeout interrupt ||
-|| 7     || IRQ_SWITCH_HOLD       || Set to enable pushbutton switch 'hold' interrupt ||
-
-For more information see [#gsc-interrupts gsc-interrupts]
-
-[=#gsc_firmware_crc]
-=== GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value
-||= Bit  =||= Description =||
-||  0-15  || Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first)[[BR]] The GSC performs a CRC check when R0.4 is set[[BR]] Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC. ||
-
-
-[=#gsc_firmware_ver]
-=== GSC_FIRMWARE_VER (Register R14): GSC Firmware Version
-||= Bit =||= Description                            =||
-|| 0-7   || Contains the GSC firmware version number ||
-
-
-[=#gsc_write_protect]
-=== GSC_WRITE_PROTECT (Register R15): Write Protection
-||= Bit =||= Name =||= Description =||
-|| 0     || GSC_EEPROM_WP_ALL || 1 = Write Protect all EEPROM regions ||
-|| 1     || GSC_EEPROM_WP_BOARDINFO || 1 = Write Protect the reserved Gateworks '''Board Info''' EEPROM section          ||
-|| 2     || Reserved || - ||
-|| 3-7   || GSC_WP_PASSWD || Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL) ||
-
-[=#gsc_reset_cause]
-=== GSC_RESET_CAUSE (Register R16): Reset Cause
-Supported on '''GSCv3 firmware v53+''', the GSC_RESET_CAUSE register describes the event that caused the boards power supply to be reset by the GSC. This register is read by up to date Newport and Venice boot firmware and displays an ASCII flag representation. See the [#reset-cause reset cause] section for more detail.
-
-||= Value =||= Name =||= ASCII Flag =||= Description =||
-|| 0  || RST_CAUSE_VIN             || VIN || Board power was cycled externally; no reset ||
-|| 1  || RST_CAUSE_PB              || PB || User pushbutton ||
-|| 2  || Reserved                  || - || - ||
-|| 3  || RST_CAUSE_CPU             || CPU || CPU watchdog ||
-|| 4  || RST_CAUSE_TEMP_LOCAL      || TEMP_L || Board Temperature exceeded spec ||
-|| 5  || RST_CAUSE_TEMP_REMOTE     || TEMP_R || CPU Temperature exceeded spec ||
-|| 6  || RST_CAUSE_SLEEP           || SLEEP || GSC woke board from sleep ||
-|| 7  || RST_CAUSE_BOOT_WDT        || BOOT_WDT1 || Boot watchdog ||
-|| 8  || RST_CAUSE_BOOT_WDT_MANUAL || BOOT_WDT2 || User pushbutton 5x to toggle boot device ||
-|| 9  || RST_CAUSE_SOFT_PWR        || SOFT_PWR || Button press from soft power control ||
-
-
-[=#GSC_INTERRUPT_SOURCE_1]
-=== GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
-
-||= Value =||= Name =||= Description =||
-|| 0 || GSP_IRQ_OVRTMP_LOCAL || When set the local temp rose above CRIT_BOARD_TEMP ||
-|| 1 || GSP_IRQ_OVRTMP_REMOTE || When set the remote temp sensor asserted its ALERTJ signal ||
-
-[=#GSC_INTERRUPT_ENABLE_1]
-=== GSC_INTERRUPT_ENABLE_1 (Register R18): Interrupt Enable 1
-
-||= Value =||= Name =||= Description =||
-|| 0 || GSP_IRQ_OVRTMP_LOCAL || Set to enable the local temp rose above CRIT_BOARD_TEMP interrupt ||
-|| 1 || GSP_IRQ_OVRTMP_REMOTE || Set to enable the remote temp sensor asserted ALERTJ signal interrupt ||
-
-[=#gsc_thermal_protect]
-=== GSC_THERMAL_PROTECT (Register R19): Thermal Protection Configuration
-Supported on '''GSCv3 firmware v53+''', the GSC_THERMAL_PROTECT register configures the thermal protection feature.
-
-||= Bit =||= Name =||= Description =||
-|| 0     || GSC_TP_ENABLE || 1 = Enable Thermal protection ||                                     
-
-[=#GSC_BOOT_OPTIONS]
-=== GSC_BOOT_OPTIONS (Register R21): Boot Control Options
-
-||= Value =||= Name =||= Description =||
-|| 0 || GSC_SWITCH_BOOT_SELECT || Boot device select. Clear for primary, set for alt device. This bit is also controlled by the [#UserPushbutton user pushbutton] 5x press behavior.  ||
-
-[=#GSC_MEM_ACCESS_PAGE]
-=== GSC_MEM_ACCESS_PAGE (Register R22): Direct Memory Access Page Number
-
-||= Value =||= Name =||= Description =||
-|| 0-7 || GSC_PAGE_NUMBER || Page address offset when direct reading the GSC flash ||
-
-This API which is implemented over I2C on address {{{0x5f}}} allows a user to do direct memory reads over the entirety of the accessible memory range ({{{0x0000-0xFFFF}}}). It is used by constructing a 16 bit address with the top byte (a.k.a. page) being set by writing to an undocumented register at address {{{0x20}}} offset {{{0x1f}}}. The bottom byte is then added on via standard I2C protocol. Memory writes are not supported with this API. In order to simplify the usage of this API, a bash script was created that will be posted on the wiki and/or given to FAE's to distribute as they see fit. The name of the script is {{{gsc_direct_mem.sh}}} and the contents are included below. 
-
- [[CollapsibleStart(GSC Direct Memory Read Script)]]
-{{{#!bash
-#!/bin/bash
-
-[ "$#" -ne 2 ] && {
-        echo "This script acts as a wrapper around I2C commands in order to do direct memory reads of the GSC."
-        echo "It will output the i2c response in an i2cdump type format."
-        echo
-        echo "Usage: $0 <offset> <length>"
-        echo
-        echo "Example usage to read all 2000(0x7d0) peripheral register values:"
-        echo "  $0 0x100 0x7d0"
-        exit 1
-}
-
-# Store inputs
-BUS=0
-ADDR=0x5e
-OFFSET=$1
-LENGTH=$2
-
-# Misc variables
-COUNT=0
-PAGE=0
-PRINTVAL=0x0000
-REMAINDER=0
-HIGH=
-RETURN=
-
-# Calculate initial page number based on passed in offset
-PAGE=$((OFFSET / 0x100))
-OFFSET=$((OFFSET % 0x100))
-
-echo "      0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f     0123456789abcdef"
-while [[ $COUNT -ne $LENGTH ]]; do
-        # Set the page number accordingly
-        i2cset -f -y 0 0x20 0x16 $PAGE
-
-        # Do either a full i2cdump or specify a range if bytes aren't a 0x100 aligned block
-        if [[ $(($LENGTH - $COUNT)) -lt 0x100 || $OFFSET -ne 0 ]]; then
-                HIGH=$(($LENGTH - $COUNT - 1 + $OFFSET))
-                # Record remainder for i2c 0x100 upper range limit
-                if [[ $HIGH -gt 0x100 ]]; then
-                        REMAINDER=$(($HIGH + 1 - 0x100))
-                else
-                        REMAINDER=0
-                fi
-
-                RETURN=$(i2cdump -f -y -r ${OFFSET}-$(($HIGH - $REMAINDER)) 0 $ADDR b | grep ':')
-                COUNT=$(($HIGH - $REMAINDER - $OFFSET + 1 + $COUNT))
-                OFFSET=0
-        else
-                RETURN=$(i2cdump -f -y 0 $ADDR b | grep ':')
-                COUNT=$(($COUNT + 0x100))
-        fi
-
-        if [[ "$RETURN" ]]; then # Only print reads
-                # Format output to be continuous and account for page increase
-                echo "$RETURN" | while read x; do
-                        printf "%04x" "$((0x$(echo $x | cut -d':' -f1) + $((PAGE * 0x100))))"
-                        echo ":${x##*:}"
-                done
-        fi
-
-        # Increase the page count
-        ((++PAGE))
-done
-}}}
-[[CollapsibleEnd]]
-
-[=#GSC_CTRL_2]
-=== GSC_CTRL_2 (Register R23): Pushbutton, Miscellaneous Configuration
-Supported in '''GSCv3 firmware v58+'''. 
-
-||= Value =||= Name =||= Description =||
-|| 0 || GSC_10X_PRESS_DISABLE || Disable 10x press for loading FACTORY registers (see [#GSC_REGISTER_BACKUP register backup]) ||
-|| 1 || GSC_SOFT_WAKE_PROTECT || Disable waking from soft power press if VIN below board preset minimum ||
-
-[=#GSC_SOFT_POWER_TIME]
-=== GSC_SOFT_POWER_TIME (Register R26): Soft Power Press Time
-Supported in '''GSCv3 firmware v58+'''. This register controls how long (in seconds) the pushbutton must be depressed before the board turns on/off via soft power control. The register is composed of an upper and lower nibble that control the minimum power on and power off press times respectively. The register defaults to a power on press time of {{{0}}} seconds and a power off press time of {{{1}}} second ({{{0x01}}}).
-
-||= Value =||= Name =||= Description =||
-|| 0-3 || GSC_SOFT_POWER_TIME_ON || Minimum pushbutton press time required to wake, in seconds ||
-|| 4-7 || GSC_SOFT_POWER_TIME_OFF || Minimum pushbutton press time required to sleep, in seconds ||
-
-[=#GSC_REGISTER_BACKUP]
-=== GSC_REGISTER_BACKUP (Register R31): Register Backup Control
-This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information.
-
-||= Value =||= Name =||= Description =||
-|| 1 || GSC_REG_BKP_SAVE || Save current register values to USER backup area ||
-|| 2 || GSC_REG_BKP_USER_LOAD || Load register values from USER backup ||
-|| 3 || GSC_REG_BKP_FACTORY_LOAD || Load register values from FACTORY backup ||
-|| 4-7 || GSC_REG_BKP_PASSWORD || Password for upper nibble ({{{0xA0}}}). Bitwise OR this value with lower nibble enumerated values described above ||
 
 [=#reg_save_load]