Changes between Version 68 and Version 69 of gsc

Timestamp:

01/05/2021 04:48:30 PM (4 years ago)

Author:

Bobby Jones

Comment:

replace interrupt "_SOURCE*" mentions with "_STATUS" for consistency

gsc

@@ -68 +68 @@
 || 2-5          || [#gsc_sleep_wake_time GSC_SLEEP_WAKE_TIME]  || Sleep Wakeup Timer                            || All ||
 || 6-9          || [#gsc_sleep_add GSC_SLEEP_ADD]        || Sleep Wakeup Additive Timer                   || All ||
-|| 10           || [#gsc_interrupt_status GSC_INTERRUPT_SOURCE_0] || Interrupt Source                              || All ||
+|| 10           || [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0] || Interrupt Source                              || All ||
 || 11           || [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0] || Interrupt Enable                              || All ||
 || 12-13        || [#gsc_firmware_crc GSC_FIRMWARE_CRC]     || Firmware CRC Value                            || All ||
@@ -74 +74 @@
 || 15           || [#gsc_write_protect GSC_WRITE_PROTECT]    || Write Protection                              || All ||
 || 16           || [#gsc_reset_cause GSC_RESET_CAUSE]      || Reset Cause                                   || GSCv3 ||
-|| 17           || [#GSC_INTERRUPT_SOURCE_1 GSC_INTERRUPT_SOURCE_1] || Interrupt Source 1                          || GSCv3 ||
+|| 17           || [#GSC_INTERRUPT_STATUS_1 GSC_INTERRUPT_STATUS_1] || Interrupt Source 1                          || GSCv3 ||
 || 18           || [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1] || Interrupt Enable 1                          || GSCv3 ||
 || 19           || [#gsc_thermal_protect GSC_THERMAL_PROTECT]  || Thermal Protection                            || GSCv3 ||
@@ -184 +184 @@
 
 
-[=#GSC_INTERRUPT_SOURCE_1]
-=== GSC_INTERRUPT_SOURCE_1 (Register R17): Interrupt Source 1
+[=#GSC_INTERRUPT_STATUS_1]
+=== GSC_INTERRUPT_STATUS_1 (Register R17): Interrupt Source 1
 
 ||= Value =||= Name =||= Description =||
@@ -967 +967 @@
 The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The [#gsc_interrupt_enable GSC_INTERRUPT_ENABLE_0 (R11)] register defines what events can trigger an interrupt and an interrupt service routine can query the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the [#gsc_interrupt_status GSC_INTERRUPT_STATUS_0 (R10)] register.
 
-'''GSCv3''' has an additional pair of interrupt registers represented by [#GSC_INTERRUPT_SOURCE_1 GSC_INTERRUPT_STATUS_1 (R17)] and [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1 (R18)].
+'''GSCv3''' has an additional pair of interrupt registers represented by [#GSC_INTERRUPT_STATUS_1 GSC_INTERRUPT_STATUS_1 (R17)] and [#GSC_INTERRUPT_ENABLE_1 GSC_INTERRUPT_ENABLE_1 (R18)].
 
 [=#IRQ_PB]
@@ -1241 +1241 @@
   - Add Venice rev B ADC rails
   - Fix irq deassertion on over temp event
-  - Prevent external setting of GSC_INTERRUPT_SOURCE_* bits
+  - Prevent external setting of GSC_INTERRUPT_STATUS_* bits
  * v57: 20200716
   - Fix issues related to updating with gsc_update