Changes between Version 71 and Version 72 of gsc
- Timestamp:
- 01/05/2021 05:42:02 PM (4 years ago)
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gsc
v71 v72 189 189 [=#GSC_INTERRUPT_STATUS_1] 190 190 === GSC_INTERRUPT_STATUS_1 (Register R17): Interrupt Source 1 191 Supported on '''GSCv3 firmware v53+'''. 191 192 192 193 ||= Value =||= Name =||= Description =|| … … 196 197 [=#GSC_INTERRUPT_ENABLE_1] 197 198 === GSC_INTERRUPT_ENABLE_1 (Register R18): Interrupt Enable 1 199 Supported on '''GSCv3 firmware v53+'''. 198 200 199 201 ||= Value =||= Name =||= Description =|| … … 210 212 [=#GSC_BOOT_OPTIONS] 211 213 === GSC_BOOT_OPTIONS (Register R21): Boot Control Options 214 Supported on '''GSCv3 firmware v57+'''. 212 215 213 216 ||= Value =||= Name =||= Description =|| … … 216 219 [=#GSC_MEM_ACCESS_PAGE] 217 220 === GSC_MEM_ACCESS_PAGE (Register R22): Direct Memory Access Page Number 221 Supported on '''GSCv3 firmware v57+'''. 218 222 219 223 ||= Value =||= Name =||= Description =|| … … 240 244 [=#GSC_REGISTER_BACKUP] 241 245 === GSC_REGISTER_BACKUP (Register R31): Register Backup Control 242 This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information.246 Supported on '''GSCv3 firmware v57+'''. This register has an upper nibble password of value {{{0xA0}}} that should be bitwise OR'd with an enumerated value in the lower nibble that will be interpreted as the command. This register will self clear when the operation has completed. See the below [#reg_save_load Register Save/Load] section for more information. 243 247 244 248 ||= Value =||= Name =||= Description =||