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Newport Digital IO
The intent of this page is to provide information about Newport single board computers off-board digital IO signals.
DIO Mapping
Newport baseboards provide 4 digital IO signals to an off-board connector. The CN81XX has a single GPIO blocks having 48 GPIO's. Note that only 32 of these are accessible on the CN80XX used on Newport boards. Each GPIO controller gets mapped to a range of Linux gpio's by the Linux kernel. Note that this mapping is not guaranteed to stay the same across kernel versions - you can look at the debugfs /sys/kernel/debug/gpio file to see where the GPIO controllers are mapped.
The various Newport product hardware manuals contain a table of what pins on the Digital IO connector routes to what CN80XX GPIO. For convenience this information is also provided in the table below.
Note that all four DIO signals contain an internal weak pulldown approximately 50kohm.
Newport GPIO Mapping:
| Board | DIO1 | Connector2 | CN80XX GPIO3 | Linux gpio 4 | Termination5 | Notes6 |
|---|---|---|---|---|---|---|
| GW640x | DIO0 | J15.1 | GPIO_24 | gpio-464 | RC/TVS termination | |
| DIO1 | J15.2 | GPIO_25 | gpio-465 | RC/TVS termination | ||
| DIO2 | J15.3 | GPIO_26 | gpio-466 | RC/TVS termination | ||
| DIO3 | J15.4 | GPIO_27 | gpio-467 | RC/TVS termination | build option exists to route to a 0-5V ADC | |
| GND | J15.5 | - | - | |||
| GW630x | DIO0 | J13.1 | GPIO_24 | gpio-464 | RC/TVS termination | |
| DIO1 | J13.2 | GPIO_25 | gpio-465 | RC/TVS termination | ||
| DIO2 | J13.3 | GPIO_26 | gpio-466 | RC/TVS termination | ||
| DIO3 | J13.4 | GPIO_27 | gpio-467 | RC/TVS termination | build option exists to route to a 0-5V ADC | |
| GND | J13.5 | - | - | |||
| GW620x | DIO0 | J10.1 | GPIO_24 | gpio-464 | RC/TVS termination | |
| DIO1 | J10.2 | GPIO_25 | gpio-465 | RC/TVS termination | ||
| DIO2 | J10.3 | GPIO_26 | gpio-466 | RC/TVS termination | build option exists to route to a 0-5V ADC | |
| DIO3 | J10.4 | GPIO_27 | gpio-467 | RC/TVS termination | build option exists to route to GSC User PB or Tamper | |
| GND | J10.5 | - | - | |||
| VDD_3P3 | J10.6 | - | - | - | 1.0Amax; build option exists to route to VDD_5P0 | |
| GW610x | DIO0 | J10.19 | GPIO_24 | gpio-464 | R termination | |
| DIO1 | J10.20 | GPIO_25 | gpio-465 | R termination | ||
| DIO2 | J10.17 | GPIO_26 | gpio-466 | R termination | ||
| DIO3 | J10.18 | GPIO_27 | gpio-467 | R termination | ||
| GND | J10.2/4/6 | - | - | |||
| VDD_3P3 | J10.1/3 | - | - | 1.0A max | ||
| VDD_5P0 | J10.5 | - | - | 1.0A max |
- This is the signal name from the Newport hardware manuals
- This is the connector pinout
- This is the GPIO as seen by the CN80XX
- This is the gpio mapped in linux accessible via
/sys/class/gpio. Note that you will have to manually export these (see gpio) - Electrical termination includes an internal ~50kohm weak pull-down as well as the following if specified:
- RC consists of a 330ohm series current limit resistor and a 390pF cap to GND
- R consists of a 330ohm series current limit resistor
- TVS consists of a 5V-3.5PF IEC6100042 Transient Voltage Suppression diode
- Build options if specified requires a Gateworks Special - contacts sales@… for details
Software GPIO Configuration
Each CN80XX GPIO can be pin-muxed to a variety of functions internal to the SoC including software controlled GPIO function (default), clock outputs, PTP (packet timestamp) outputs, UART TX/RX/DTR/RTS, SATA activity LED, additional SPI chip selects. For more detail on this, consult the Cavium Board Diagnostics Kit source code and/or the Cavium CN80XX Hardware Manual (obtained from Cavium under NDA).
Please visit this link to find out more information about using GPIO's in Linux
Configuring GPIO Hardware
The CN80XX GPIO signals do not have the ability to configure their drive strength or other I/O characteristics.
