Changes between Version 5 and Version 6 of newport/PCIe
- 03/08/2019 05:32:33 PM (5 years ago)
v5 v6 35 35 [=#throughput] 36 36 == PCIe Throughput == 37 The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0G bits/sec) however this requires a higher co-processor speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 was made because it saves approximately 500mW of power consumption and the lack of Gen3PCIe card availability. 37 The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0GPCIe card availability. 38 38 39 By default Newport boards support PCI Gen2 (5.0G bits/sec) and are backwards compatible with PCI Gen1 (2.5Gbits/sec). 39 By default Newport boards support PCI Gen2 (5.0G). 40 40 41 If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GBits/sec) please contact firstname.lastname@example.org. 41 If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GGT/sec or 6.4Gbps) please contact email@example.com. A resistor modification is required on the board to do move SCLK from 350MHz to 550Mhz. 42 43 Note that the GW640x boards have a coprocessor clock running at 550MHz but still configure PCIe for Gen2 rates. Therefore on a GW640x you can modify the QLM-FREQ.N0.QLM* proprety in BDK device-tree file bdk/boards/gw6404.dtsi to specify 8000 MHz for Gen3. 42 44 43 45 The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.