Newport PCI/PCIe Support

The CN80XX/CN81XX has three PEM's (PCI Express Interface) internally which are routed to MiniPCIe socket's depending on board and Bootloader configuration (see hwconfig).

CN80XX/CN81XX PEM Features:

• PCIe root complex (RC) support
• PCIe Specification v3.0 compliant
• dedicated reset pin per port/controller
• PCIe memory-space master support:
  • 256 separate 32bit windows available for direct core access to PCIe memory space in Switch Logic Interface Unit (SLI)
    • Programmable store merging
    • Regions can be combined to form up to a 40bit window
  • Direct core PCIe I/O space and configuration space request generation windows in SLI
  • ECAM support
• Dected PCIe support summary:
  • Max_Payload_Size up to 256 bytes
  • Readcompletion boundary of 128 bytes
  • ECRC implemented
  • MSI-X implemented for both SR-IOV and non-SR-IOV configurations
  • ASPM support for both L0s and L1 (DLM/PHY power might not be reduced in these states but the power consumed by the link partner may be)
  • Extended tag supported
  • Atomic operations (both 32bit and 64bit CAS, FADD and SWAP)

Mini-PCIe Routing Configuration

Each slot can be configured to be either PCIe, SATA, or USB3. To configure the slots, read about hwconfig

PCIe Pinout

Please see the user manuals ​here

PCIe Throughput

The CN80XX/CN81XX PCIe host supports up to PCI Gen3 (8.0GT/sec or 6.4Gbps) however this requires a higher co-processor (SCLK) speed (550MHz) than is configured by default (350MHz) on standard Newport boards. This is a resistor loading option thus can't be changed by software. The decision to default to 350MHz supporting Gen2 (5.0GT/sec or 4Gbps) was made because it saves approximately 500mW of power consumption and the lack of Gen3 miniPCIe card availability.

By default Newport boards support PCI Gen2 (5.0GHz/sec or 4Gbps) which is backwards compatible with PCI Gen1 (2.5GT/sec or 2Gbps).

If you are interested in utilizing PCIe cards up to Gen3 performance (8.0GGT/sec or 6.4Gbps) please contact sales@…. A resistor modification is required on the board to do move SCLK from 350MHz to 550Mhz.

Note that the GW640x boards have a coprocessor clock running at 550MHz but still configure PCIe for Gen2 rates. Therefore on a GW640x you can modify the QLM-FREQ.N0.QLM* proprety in BDK device-tree file bdk/boards/gw6404.dtsi to specify 8000 MHz for Gen3.

The bus speed represents a theoretical maximum throughput and does not account for host processing speed or bus contention from multiple masters.

PCIe Reset

PCI Reset signals (PERST#) are routed to the Mini-PCIe slots.

On the Newport boards each Mini-PCIe socket has its own dedicated PCI Reset (PERST#) signal.

Mini-PCIe Mechanical Specification

Please see here: Mini-PCIe Mechanical

See also

• PCI
• ventana/PCIe