Changes between Version 1 and Version 2 of sbcrevisions


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Timestamp:
10/22/2017 06:28:19 AM (8 years ago)
Author:
Chris Lang
Comment:

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  • sbcrevisions

    v1 v2  
    1 = Gateworks Single Board Computers Revisions =
    2 [[PageOutline]]
     1{{{#!html       
     2          <div id="wikipage" class="trac-content"><h1 id="GateworksSingleBoardComputersRevisions">Gateworks Single Board Computers Revisions</h1>
     3<p>
     4</p><div class="wiki-toc">
     5<ol>
     6  <li>
     7    <a href="#GateworksSingleBoardComputersRevisions">Gateworks Single Board Computers Revisions</a>
     8  </li>
     9  <li>
     10    <a href="#VentanaFamily">Ventana Family</a>
     11    <ol>
     12      <li>
     13        <a href="#GW51xx">GW51xx</a>
     14        <ol>
     15          <li>
     16            <a href="#RevisionA">Revision A</a>
     17          </li>
     18          <li>
     19            <a href="#RevisionB">Revision B</a>
     20          </li>
     21          <li>
     22            <a href="#RevisionB.1">Revision B.1</a>
     23          </li>
     24          <li>
     25            <a href="#RevisionC">Revision C</a>
     26          </li>
     27          <li>
     28            <a href="#RevisionD">Revision D</a>
     29          </li>
     30          <li>
     31            <a href="#RevisionE.1">Revision E.1</a>
     32          </li>
     33          <li>
     34            <a href="#RevisionF">Revision F</a>
     35          </li>
     36        </ol>
     37      </li>
     38      <li>
     39        <a href="#GW520x">GW520x</a>
     40        <ol>
     41          <li>
     42            <a href="#RevisionA1">Revision A</a>
     43          </li>
     44          <li>
     45            <a href="#RevisionA.1">Revision A.1</a>
     46          </li>
     47          <li>
     48            <a href="#RevisionB.11">Revision B.1</a>
     49          </li>
     50          <li>
     51            <a href="#RevisionC.1">Revision C.1</a>
     52          </li>
     53          <li>
     54            <a href="#RevisionC.2">Revision C.2</a>
     55          </li>
     56          <li>
     57            <a href="#RevisionD1">Revision D</a>
     58          </li>
     59        </ol>
     60      </li>
     61      <li>
     62        <a href="#GW522x">GW522x</a>
     63        <ol>
     64          <li>
     65            <a href="#RevisionA2">Revision A</a>
     66          </li>
     67          <li>
     68            <a href="#RevisionA.11">Revision A.1</a>
     69          </li>
     70          <li>
     71            <a href="#RevisionB1">Revision B</a>
     72          </li>
     73          <li>
     74            <a href="#RevisionC1">Revision C</a>
     75          </li>
     76          <li>
     77            <a href="#RevisionD2">Revision D</a>
     78          </li>
     79          <li>
     80            <a href="#RevisionD.1">Revision D.1</a>
     81          </li>
     82        </ol>
     83      </li>
     84      <li>
     85        <a href="#GW53xx">GW53xx</a>
     86        <ol>
     87          <li>
     88            <a href="#RevisionA3">Revision A</a>
     89          </li>
     90          <li>
     91            <a href="#RevisionA.12">Revision A.1</a>
     92          </li>
     93          <li>
     94            <a href="#RevisionB2">Revision B</a>
     95          </li>
     96          <li>
     97            <a href="#RevisionC2">Revision C</a>
     98          </li>
     99          <li>
     100            <a href="#RevisionD3">Revision D</a>
     101          </li>
     102          <li>
     103            <a href="#RevisionE">Revision E</a>
     104          </li>
     105          <li>
     106            <a href="#RevisionF1">Revision F</a>
     107          </li>
     108        </ol>
     109      </li>
     110      <li>
     111        <a href="#GW54xx">GW54xx</a>
     112        <ol>
     113          <li>
     114            <a href="#RevisionB3">Revision B</a>
     115          </li>
     116          <li>
     117            <a href="#RevisionC3">Revision C</a>
     118          </li>
     119          <li>
     120            <a href="#RevisionD4">Revision D</a>
     121          </li>
     122          <li>
     123            <a href="#RevisionE1">Revision E</a>
     124          </li>
     125          <li>
     126            <a href="#RevisionE.11">Revision E.1</a>
     127          </li>
     128          <li>
     129            <a href="#RevisionF2">Revision F</a>
     130          </li>
     131        </ol>
     132      </li>
     133      <li>
     134        <a href="#GW551x">GW551x</a>
     135        <ol>
     136          <li>
     137            <a href="#RevisionA.13">Revision A.1</a>
     138          </li>
     139          <li>
     140            <a href="#RevisionB4">Revision B</a>
     141          </li>
     142          <li>
     143            <a href="#RevisionC4">Revision C</a>
     144          </li>
     145          <li>
     146            <a href="#RevisionC.11">Revision C.1</a>
     147          </li>
     148          <li>
     149            <a href="#RevisionD5">Revision D</a>
     150          </li>
     151        </ol>
     152      </li>
     153      <li>
     154        <a href="#GW552x">GW552x</a>
     155        <ol>
     156          <li>
     157            <a href="#RevisionA.2">Revision A.2</a>
     158          </li>
     159          <li>
     160            <a href="#RevisionB5">Revision B</a>
     161          </li>
     162          <li>
     163            <a href="#RevisionC5">Revision C</a>
     164          </li>
     165          <li>
     166            <a href="#RevisionC.12">Revision C.1</a>
     167          </li>
     168        </ol>
     169      </li>
     170      <li>
     171        <a href="#GW553x">GW553x</a>
     172        <ol>
     173          <li>
     174            <a href="#RevisionB6">Revision B</a>
     175          </li>
     176        </ol>
     177      </li>
     178    </ol>
     179  </li>
     180  <li>
     181    <a href="#LagunaFamily">Laguna Family</a>
     182    <ol>
     183      <li>
     184        <a href="#GW2388">GW2388</a>
     185      </li>
     186    </ol>
     187  </li>
     188  <li>
     189    <a href="#OtherSBCFamilies">Other SBC Families</a>
     190  </li>
     191</ol>
     192</div><p>
     193</p>
     194<p>
     195This page is to describe the difference between hardware revisions.
     196</p>
     197<h1 id="VentanaFamily">Ventana Family</h1>
     198<h2 id="GW51xx">GW51xx</h2>
     199<h3 id="RevisionA">Revision A</h3>
     200<p>
     201Date: 04/19/2013
     202</p>
     203<ul><li>Initial release
     204</li></ul><h3 id="RevisionB">Revision B</h3>
     205<p>
     206Date: 09/17/2013
     207</p>
     208<ul><li>Add VDD_HIGH to GSC analog input for voltage monitoring
     209</li><li>Select GPS 4800 baud NMEA protocol by default
     210</li><li>Reduce voltage drop for USB OTG VBUS
     211</li><li>Adjust 5V boost converter feedback resistors for more accurate 5V
     212</li><li>Add i.MX6 GPIO control of mini-PCIe <a class="missing wiki">WiFi?</a> disable
     213</li><li>Move mounting holes to match other Ventana boards
     214</li><li>Improve HDMI and OTG connectors footprints
     215</li><li>Modify JTAG route from a star to a daisy chain topology
     216</li></ul><h3 id="RevisionB.1">Revision B.1</h3>
     217<p>
     218Date: 11/08/2013
     219</p>
     220<ul><li>Eliminate possible high input voltage on the switching supply enable input by removing unnecessary R34 pullup
     221</li></ul><h3 id="RevisionC">Revision C</h3>
     222<p>
     223Date: 09/04/2014
     224</p>
     225<ul><li>Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see <a class="wiki" href="/wiki/ventana/errata#hw8">Errata HW8</a>)
     226</li><li>Connect GPS PPS signal to reserved pin 49 on Mini-PCIe socket through unloaded configuration resistor
     227</li><li>Change GSC VDD_HIGH connection to include a divide-by-two resistive divider since voltage exceeds analog-to-digital converter 2.5V reference
     228</li><li>Add GSC analog input option to DIO
     229</li><li>Replace U15 input power supply to increase operating voltage range and improved manufacturability
     230</li><li>Ground RTC XTAL input to eliminate noise causing pre-mature watchdog resets (see <a class="wiki" href="/wiki/ventana/errata#hw7">Errata HW7</a>)
     231</li></ul><p>
     232 
     233</p>
     234<h3 id="RevisionD">Revision D</h3>
     235<p>
     236Date: 03/05/2015
     237</p>
     238<ul><li>Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
     239</li><li>Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
     240</li><li>Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     241</li><li>Reduce PORJ pullup resistor value for faster rise time
     242</li><li>Improve inductor footprints for improved manufacturability
     243</li></ul><h3 id="RevisionE.1">Revision E.1</h3>
     244<p>
     245Date: 12/23/2015
     246</p>
     247<ul><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     248</li><li>Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     249</li><li>Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
     250</li></ul><h3 id="RevisionF">Revision F</h3>
     251<p>
     252Date: 10/17/2016:
     253</p>
     254<ul><li>Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
     255</li><li>Replaced GbE crystal for increased lifespan
     256</li></ul><h2 id="GW520x">GW520x</h2>
     257<h3 id="RevisionA1">Revision A</h3>
     258<p>
     259Date: 10/18/2013
     260</p>
     261<ul><li>Initial Release
     262</li></ul><h3 id="RevisionA.1">Revision A.1</h3>
     263<p>
     264Date: 10/18/2013
     265</p>
     266<ul><li>Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance.
     267</li></ul><h3 id="RevisionB.11">Revision B.1</h3>
     268<p>
     269Date: 1/30/2014
     270</p>
     271<ul><li>Add WiFi disable signal to all Mini-PCIe sockets through zero ohm resistors
     272</li><li>Add optional load JST 1x2x2mm connector under the pushbutton switch
     273</li><li>Add ability to route USB OTG to miniPCIe socket instead of front-panel via GPIO
     274</li><li>Replace 2-pin tamper switch connector with 3-pin connector to support CAN Bus, RS485, TTL serial and tamper switch option
     275</li><li>Add optional CAN Bus transceiver
     276</li><li>Add optional RS485 transceiver
     277</li><li>Add optional TTL serial bypass resistors
     278</li><li>Add option for 3.3V and 5V power to one pin of the digital I/O connector through unloaded configuration resistors
     279</li></ul><h3 id="RevisionC.1">Revision C.1</h3>
     280<p>
     281Date: 3/31/2015
     282</p>
     283<ul><li>Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
     284</li><li>Replace 3.3V TVS arrays with 2.5V arrays for improved protection
     285</li><li>Add 3.3V voltage translator to both 2.5V PCISKTx_RSTJ signals for increased voltage margin
     286</li><li>Remove capacitor on tamper switch input to reduce switch debounce time constant
     287</li><li>Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in
     288</li><li>Connect I2C3 bus to the digital I/O connector through unloaded configuration resistors
     289</li><li>Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets through unloaded configuration resistors
     290</li><li>Add changes to support SOM application, (a) add CAN bus transceiver bypass resistors, (b) add RS232 transceiver bypass resistors, (c) add connector under uSD/SIM socket to support SD, USB, battery voltage, and reset, (d) add 2-pin power input connector
     291</li><li>Add "USB" to PCIe socket silkscreen for clarification
     292</li></ul><h3 id="RevisionC.2">Revision C.2</h3>
     293<p>
     294Date: 4/3/2015
     295</p>
     296<ul><li>Add 100 ohm differential PCIe clock termination resistor for improved PCIe clock compliance.
     297</li></ul><h3 id="RevisionD1">Revision D</h3>
     298<p>
     299Date: 2/18/2016
     300</p>
     301<ul><li>Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
     302</li><li>Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     303</li><li>Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J11.5 as an option
     304</li><li>Add optional GSC analog input to J4.1 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
     305</li><li>Add optional 4-pin friction latching connector for micro-B OTG connector
     306</li><li>Add optional OTG ID pulldown resistor to configure OTG port for host operation when optional 4-pin connector is loaded
     307</li><li>Reduce PORJ pullup resistor value for faster rise time
     308</li><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     309</li><li>Add processor watchdog support by connecting WDOG_B to PMIC PWRON input
     310</li><li>Add support for UHS-1 MMC cards to run at their full speed capability
     311</li><li>Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input
     312</li><li>Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
     313</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     314</li><li>Update SIM/uSD socket footprint and move 0.2mm closer to board edge for improved manufacturing
     315</li><li>Move USB signals away from SIM/uSD mounting tab slot to improve fabrication processes
     316</li></ul><h2 id="GW522x">GW522x</h2>
     317<h3 id="RevisionA2">Revision A</h3>
     318<p>
     319Date: 01/29/2015
     320</p>
     321<ul><li>Initial release
     322</li></ul><h3 id="RevisionA.11">Revision A.1</h3>
     323<p>
     324Date: 04/21/2015
     325</p>
     326<ul><li>Improve PCIe clock termination
     327</li></ul><h3 id="RevisionB1">Revision B</h3>
     328<p>
     329Date: 04/29/2015
     330</p>
     331<ul><li>Reduce PORJ pullup resistor value for faster rise time
     332</li><li>Improve PCIe clock termination
     333</li><li>Add processor watchdog support by connecting WDOG_B to PMIC PWRON input (see <a class="wiki" href="/wiki/ventana/errata#hw12">Errata HW12</a>)
     334</li><li>Add support for UHS-1 MMC cards to run at their full speed capability (see <a class="wiki" href="/wiki/ventana/errata#hw16">Errata HW16</a>)
     335</li><li>Correct the SPI connector bottom side silkscreen pin labels
     336</li></ul><h3 id="RevisionC1">Revision C</h3>
     337<p>
     338Date: 07/22/2015
     339</p>
     340<ul><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     341</li><li>Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     342</li><li>Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
     343</li><li>Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
     344</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     345</li></ul><h3 id="RevisionD2">Revision D</h3>
     346<p>
     347Date: 01/04/2017:
     348</p>
     349<ul><li>Add wide range linear regulator for powering the GSC battery from the input voltage when board power is turned off to extend battery life
     350</li><li>Add option for external GSC battery connector
     351</li><li>Replaced GbE crystal for increased lifespan
     352</li></ul><h3 id="RevisionD.1">Revision D.1</h3>
     353<p>
     354Date: 01/06/2017:
     355</p>
     356<ul><li>Add LDO output capacitor.
     357</li></ul><h2 id="GW53xx">GW53xx</h2>
     358<h3 id="RevisionA3">Revision A</h3>
     359<p>
     360Date: 12/17/2013
     361</p>
     362<ul><li>Initial revision
     363</li></ul><h3 id="RevisionA.12">Revision A.1</h3>
     364<p>
     365Date: 12/17/2013
     366</p>
     367<ul><li>Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance
     368</li></ul><h3 id="RevisionB2">Revision B</h3>
     369<p>
     370Date: 12/05/2013
     371</p>
     372<ul><li>Add resistor load option for I2C support via DIO connector
     373</li></ul><h3 id="RevisionC2">Revision C</h3>
     374<p>
     375Date: 07/29/2015
     376</p>
     377<ul><li>Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
     378</li><li>Improved RJ45 TVS arrays
     379</li><li>Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
     380</li><li>Remove capacitor on tamper switch input to reduce switch debounce time constant (see <a class="wiki" href="/wiki/ventana/errata#hw4">Errata HW4</a>)
     381</li><li>Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in (see <a class="wiki" href="/wiki/ventana/errata#hw8">Errata HW8</a>)
     382</li><li>Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets pin 49 through unloaded configuration resistors
     383</li><li>Add optional GSC analog input to J10.4 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
     384</li><li>Increase USB boost converter power to 1.6A max current (see <a class="wiki" href="/wiki/ventana/errata#hw6">Errata HW6</a>)
     385</li></ul><h3 id="RevisionD3">Revision D</h3>
     386<p>
     387Date: 10/10/2014
     388</p>
     389<ul><li>Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
     390</li><li>Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     391</li><li>Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default and audio connector as an option
     392</li><li>Add option to bypass CAN bus transceiver to provide additional TTL UARt
     393</li><li>Add option to bypass RS232 transceiver
     394</li></ul><h3 id="RevisionE">Revision E</h3>
     395<p>
     396Date: 03/31/2015
     397</p>
     398<ul><li>Reduce PORJ pullup resistor value for faster rise time
     399</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     400</li><li>Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     401</li><li>Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
     402</li><li>Add support for UHS-1 MMC cards to run at their full speed capability (see <a class="wiki" href="/wiki/ventana/errata#hw16">Errata HW16</a>)
     403</li></ul><h3 id="RevisionF1">Revision F</h3>
     404<ul><li>Improve 5V Boost Supply for powering CAN, HDMI, and LVDS. (see Resolves <a class="wiki" href="/wiki/ventana/errata#HW18GW53xx-CDE5Vinrushcurrentlimitedat100mA">Errata HW18</a>
     405</li><li>Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
     406</li><li>Improve voltage rails with larger traces and capacitors for greater stability when operating in LDO-Bypass mode
     407</li><li>Improve USB host connector durability
     408</li></ul><h2 id="GW54xx">GW54xx</h2>
     409<h3 id="RevisionB3">Revision B</h3>
     410<p>
     411Date: 03/14/2013
     412</p>
     413<ul><li>Initial Revision
     414</li></ul><h3 id="RevisionC3">Revision C</h3>
     415<p>
     416Date: 07/16/2013
     417</p>
     418<ul><li>Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
     419</li><li>Fix Analog Video input functionality (see <a class="wiki" href="/wiki/ventana/errata#hw1">Errata HW1</a>)
     420</li><li>Fix GPS Antenna Short Protection (see <a class="wiki" href="/wiki/ventana/errata#hw2">Errata HW2</a>)
     421</li><li>Replace MMA8451 accelerometer with FXOS8700 accelerometer/magnetometer
     422</li><li>Replace GSP with Wi2Wi Wi2Wi W2SG0008i for improved functionality
     423</li><li>Replace UART handshake with additional UART tx/rx and made previous hardware handshaking a resistor loading option
     424</li></ul><h3 id="RevisionD4">Revision D</h3>
     425<p>
     426Date: 01/13/2014
     427</p>
     428<ul><li>Add optional serial console bypass to the RS485 connector
     429</li><li>Add PoE diodes to second Ethernet connector for increased functionality
     430</li><li>Add i.MX6 GPIO control of mini-PCIe <a class="missing wiki">WiFi?</a> disable
     431</li><li>Add installed SIM card outline to silkscreen for ease of use
     432</li></ul><h3 id="RevisionE1">Revision E</h3>
     433<p>
     434Date: 6/28/2016:
     435</p>
     436<ul><li>Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see <a class="wiki" href="/wiki/ventana/errata#hw8">Errata HW8</a>)
     437</li><li>Connect GPS PPS signal to reserved pin 49 of J9 (Top right) and J10 (Bottomr left/center) Mini-PCIe sockets through unloaded configuration resistors as a build option
     438</li><li>Add 3.3V voltage translator to miniPCIe socket PERST# signals for increased voltage margin
     439</li><li>Unload capacitor C473 to resolve issue with off-board tamper signal (see  <a class="wiki" href="/wiki/ventana/errata#hw4">Errata HW4</a>)
     440</li><li>Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     441</li><li>Add ability to bypass CAN transceiver through loadable resistors
     442</li><li>Add ability to bypass UART2 RS232 transceiver through loadable resistors
     443</li><li>Improved GPS Antenna short circuit fault monitoring by lowering trip threshold to allow for higher power active antennas
     444</li><li>Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J28.5 as an option
     445</li><li>Add 0 to 5V GSC analog input available via 3-byte register at 0x1A to previously unused J27.4 connector
     446</li><li>Add resistor loading option to provide 3.3V to J16.3
     447</li><li>Add resistor loading option to provide 5.0V to J16.4
     448</li><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     449</li><li>Add processor watchdog support by connecting WDOG2_B to PMIC PWRON input (see <a class="wiki" href="/wiki/ventana/errata#hw12">Errata HW12</a>)
     450</li><li>Reduce PCIe clock jitter to GEN2 levels by routing clock generator output back to processor PCIe clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     451</li><li>Add support for UHS-1 MMC cards to run at their full speed capability (see <a class="wiki" href="/wiki/ventana/errata#hw16">Errata HW16</a>)
     452</li><li>Add a reset generator to improve signalling during board reset
     453</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills for greater stability when operating in LDO-Bypass mode as well as supporting higher frequency processors
     454</li><li>Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
     455</li><li>Improve USB host connector durability
     456</li><li>Add SPI support via J32 ((ECSPI2 SS0) (see <a class="wiki" href="/wiki/SPI">SPI</a>))
     457</li></ul><h3 id="RevisionE.11">Revision E.1</h3>
     458<p>
     459Date: 6/29/2016:
     460</p>
     461<ul><li>Increase VDD_1P8 current flow with soldered wire
     462</li></ul><h3 id="RevisionF2">Revision F</h3>
     463<p>
     464Date: 11/01/2016:
     465</p>
     466<ul><li>Increase VDD_1P8 trace width to remove need for wire from Revision E.1
     467</li></ul><h2 id="GW551x">GW551x</h2>
     468<h3 id="RevisionA.13">Revision A.1</h3>
     469<p>
     470Date: 01/08/2015
     471</p>
     472<ul><li>Initial release
     473</li></ul><h3 id="RevisionB4">Revision B</h3>
     474<p>
     475Date: 02/18/2015
     476</p>
     477<ul><li>Move passives further from mounting holes
     478</li><li>Increase spacing between the HDMI input and HDMI output connectors
     479</li><li>Reduce PORJ pullup resistor value for faster rise time
     480</li><li>Improve HDMI video input to allow YUV422 semi-planar input allowing 1080p@60Hz (see <a class="wiki" href="/wiki/ventana/errata#hw9">Errata HW9</a>)
     481</li><li>Fix USB OTG device mode (see <a class="wiki" href="/wiki/ventana/errata#hw10">Errata HW10</a>)
     482</li></ul><h3 id="RevisionC4">Revision C</h3>
     483<p>
     484Date: 10/06/2016:
     485</p>
     486<ul><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     487</li><li>Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input (see [<a class="wiki" href="/wiki/ventana/errata#hw12">wiki:ventana/errata#hw12</a> Errata HW12)
     488</li><li>Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     489</li><li>Adjust processor drive on CPU crystal for increased lifespan
     490</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     491</li></ul><h3 id="RevisionC.11">Revision C.1</h3>
     492<p>
     493Date: 02/10/2017:
     494</p>
     495<ul><li>Fix HS/CLK on HDMI Input
     496</li></ul><h3 id="RevisionD5">Revision D</h3>
     497<p>
     498Date: 03/02/2017:
     499</p>
     500<ul><li>Fix YUV422 semi-planar HDMI input to support 1080p60
     501</li></ul><h2 id="GW552x">GW552x</h2>
     502<h3 id="RevisionA.2">Revision A.2</h3>
     503<p>
     504Date: 11/19/2014
     505</p>
     506<ul><li>Initial release
     507</li></ul><h3 id="RevisionB5">Revision B</h3>
     508<p>
     509Date: 07/29/2015
     510</p>
     511<ul><li>Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see <a class="wiki" href="/wiki/ventana/errata#hw8">Errata HW8</a>)
     512</li><li>Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
     513</li><li>Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
     514</li><li>Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
     515</li><li>move barrel jack to the opposite side of the power supply to eliminate interface between HDMI and barrel jack mating connectors
     516</li><li>add software controllable USB switch to configure one of the panel USB ports for either host or device
     517</li></ul><h3 id="RevisionC5">Revision C</h3>
     518<p>
     519Date: 03/29/2016
     520</p>
     521<ul><li>Reduce PORJ pullup resistor value for faster rise time
     522</li><li>Add series resistor between battery positive and reverse current diode for UL two level protection
     523</li><li>Adjust processor drive on CPU crystal for increased lifespan
     524</li><li>Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
     525</li><li>Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
     526</li><li>Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see <a class="wiki" href="/wiki/ventana/errata#hw14">Errata HW14</a>)
     527</li><li>Add resistor load option for SPI support via J8 ((ECSPI3 J8.1:SS0# J8.2:SCLK, J8.17:MOSI, J8.18:MISO see <a class="wiki" href="/wiki/SPI">SPI</a>))
     528</li><li>Add resistor load option for I2C support via J8 ((I2C3: J8.17:SCL, J8.18:SDA))
     529</li><li>Move battery to reduce heat impact on it's lifespan
     530</li><li>Replace J8 10pin connector with 20pin connector
     531</li></ul><h3 id="RevisionC.12">Revision C.1</h3>
     532<p>
     533Date: 10/18/2016
     534</p>
     535<ul><li>Replace J8 20pin connector with 10pin connector (20pin connector available as option)
     536</li></ul><h2 id="GW553x">GW553x</h2>
     537<h3 id="RevisionB6">Revision B</h3>
     538<p>
     539Date: 08/30/2016
     540</p>
     541<ul><li>Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
     542</li><li>Replace 2-pin connector with reset switch for standard product (2-pin connector is optional)
     543</li><li>Replace 2-pin connector with user LED (2-pin connector is optional)
     544</li></ul><h1 id="LagunaFamily">Laguna Family</h1>
     545<h2 id="GW2388">GW2388</h2>
     546<p>
     547Please see <a class="ext-link" href="http://www.gateworks.com/usermanuals"><span class="icon">​</span>GW2388 User Manual</a> and view revision notes at the end.
     548</p>
     549<p>
     550Please contact support
     551</p>
     552<h1 id="OtherSBCFamilies">Other SBC Families</h1>
     553<p>
     554Please contact support
     555</p>
    3556
    4 This page is to describe the difference between hardware revisions.
    5 
    6 = Ventana Family =
    7 
    8 == GW51xx ==
    9 
    10 == GW520x ==
    11 === Revision A ===
    12 Date: 10/18/2013
    13 
    14  * Initial Release
    15 
    16 === Revision A.1 ===
    17 Date: 10/18/2013
    18  * Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance.
    19 
    20 === Revision B.1 ===
    21 Date: 1/30/2014
    22  * Add !WiFi disable signal to all Mini-PCIe sockets through zero ohm resistors
    23  * Add optional load JST 1x2x2mm connector under the pushbutton switch
    24  * Add ability to route USB OTG to miniPCIe socket instead of front-panel via GPIO
    25  * Replace 2-pin tamper switch connector with 3-pin connector to support CAN Bus, RS485, TTL serial and tamper switch option
    26  * Add optional CAN Bus transceiver
    27  * Add optional RS485 transceiver
    28  * Add optional TTL serial bypass resistors
    29  * Add option for 3.3V and 5V power to one pin of the digital I/O connector through unloaded configuration resistors
    30 
    31 === Revision C.1 ===
    32 Date: 3/31/2015
    33  * Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
    34  * Replace 3.3V TVS arrays with 2.5V arrays for improved protection
    35  * Add 3.3V voltage translator to both 2.5V PCISKTx_RSTJ signals for increased voltage margin
    36  * Remove capacitor on tamper switch input to reduce switch debounce time constant
    37  * Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in
    38  * Connect I2C3 bus to the digital I/O connector through unloaded configuration resistors
    39  * Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets through unloaded configuration resistors
    40  * Add changes to support SOM application, (a) add CAN bus transceiver bypass resistors, (b) add RS232 transceiver bypass resistors, (c) add connector under uSD/SIM socket to support SD, USB, battery voltage, and reset, (d) add 2-pin power input connector
    41  * Add "USB" to PCIe socket silkscreen for clarification
    42 
    43 === Revision C.2  ===
    44 Date: 4/3/2015
    45  * Add 100 ohm differential PCIe clock termination resistor for improved PCIe clock compliance.
    46 
    47 === Revision D  ===
    48 Date: 2/18/2016
    49  * Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
    50  * Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
    51  * Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J11.5 as an option
    52  * Add optional GSC analog input to J4.1 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
    53  * Add optional 4-pin friction latching connector for micro-B OTG connector
    54  * Add optional OTG ID pulldown resistor to configure OTG port for host operation when optional 4-pin connector is loaded
    55  * Reduce PORJ pullup resistor value for faster rise time
    56  * Add series resistor between battery positive and reverse current diode for UL two level protection
    57  * Add processor watchdog support by connecting WDOG_B to PMIC PWRON input
    58  * Add support for UHS-1 MMC cards to run at their full speed capability
    59  * Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input
    60  * Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
    61  * Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
    62  * Update SIM/uSD socket footprint and move 0.2mm closer to board edge for improved manufacturing
    63  * Move USB signals away from SIM/uSD mounting tab slot to improve fabrication processes
    64 
    65 
    66 
    67 == GW53xx ==
    68 === Revision F ===
    69  * Improve 5V Boost Supply for powering CAN, HDMI, and LVDS. (see Resolves [wiki:ventana/errata#HW18GW53xx-CDE5Vinrushcurrentlimitedat100mA Errata HW18]
    70  * Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
    71  * Improve voltage rails with larger traces and capacitors for greater stability when operating in LDO-Bypass mode
    72  * Improve USB host connector durability
    73 
    74 == GW54xx ==
    75 
    76 === Revision E ===
    77 Date: 6/28/2016:
    78  * Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see [wiki:ventana/errata#hw8 Errata HW8])
    79  * Connect GPS PPS signal to reserved pin 49 of J9 (Top right) and J10 (Bottomr left/center) Mini-PCIe sockets through unloaded configuration resistors as a build option
    80  * Add 3.3V voltage translator to miniPCIe socket PERST# signals for increased voltage margin
    81  * Unload capacitor C473 to resolve issue with off-board tamper signal (see  [wiki:ventana/errata#hw4 Errata HW4])
    82  * Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
    83  * Add ability to bypass CAN transceiver through loadable resistors
    84  * Add ability to bypass UART2 RS232 transceiver through loadable resistors
    85  * Improved GPS Antenna short circuit fault monitoring by lowering trip threshold to allow for higher power active antennas
    86  * Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J28.5 as an option
    87  * Add 0 to 5V GSC analog input available via 3-byte register at 0x1A to previously unused J27.4 connector
    88  * Add resistor loading option to provide 3.3V to J16.3
    89  * Add resistor loading option to provide 5.0V to J16.4
    90  * Add series resistor between battery positive and reverse current diode for UL two level protection
    91  * Add processor watchdog support by connecting WDOG2_B to PMIC PWRON input (see [wiki:ventana/errata#hw12 Errata HW12])
    92  * Reduce PCIe clock jitter to GEN2 levels by routing clock generator output back to processor PCIe clock input (see [wiki:ventana/errata#hw14 Errata HW14])
    93  * Add support for UHS-1 MMC cards to run at their full speed capability (see [wiki:ventana/errata#hw16 Errata HW16])
    94  * Add a reset generator to improve signalling during board reset
    95  * Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills for greater stability when operating in LDO-Bypass mode as well as supporting higher frequency processors
    96  * Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
    97  * Improve USB host connector durability
    98  * Add SPI support via J32
    99 
    100 == GW551x ==
    101 
    102 == GW552x ==
    103 
    104 = Laguna Family =
    105 
    106 Please contact support
    107 
    108 = Other SBC Families =
    109 
    110 Please contact support
     557}}}