Gateworks Single Board Computers Revisions

This page is to describe the difference between hardware revisions.

Venice Family

Most of the Venice family is comprised of a base board and a SOM (system on module). Each component can have it's own revision, therefore the scheme used for products is as follows:

• Example: GW7301-01-DF
• The first part of the model number is the baseboard, the GW7301
• The second 2 digits are the last 2 digits of the SOM model number. In this case, the SOM would be 7001.
• The last 2 letters denote the revisions of each component, with the baseboard first followed by the SOM. So the baseboard is revision D while the SOM is revision F.

GW71xx Baseboard

Revision A

Date: 2021-06-02

• Initial release

Revision B

Date: 2021-10-08

• Improve power supply protection for up to 60V DC input
• Increase primary 5V power supply limit to 7.5A
• Move battery socket slightly away from board edge
• Always enable the USB power switch controller (elimate need for software workaround)

Revision C

Date: 2022-03-08

• Replace all Active PoE/test connector diodes with available parts, due to supply chain challenges
• Update TVS diode to bidirectional and move on connector side of reverse protection diode.
• Add additional footprint for LIS2MDL magnetometer as optional load.
• Do not load magnetic capacitors per the RGMII Phy datasheet.
• Replace surface mount RJ45 with through hole part to increase connector durability. This results in some location changes of diodes and capacitors on the bottom side of the PCB.

Revision D

Date: 2022-06-08

• Improve ESD protection to the GPY111 Phy
• Add optional mounting hole ground resistors to H2 and H4

Revision E

Date: 2023-12-08

• Add optional resistors to Mini-PCIe socket for V2X radio
• Tie USDHC2_NVCC (J7.36) to 3.3V
• Add optional pullup resistors for the I2C and SPI lines if needed to repurpose to GPIOs
• Adjust voltage divider for GSC_ADC1 (10k/10k)
• Resolve Venice Errata VN8
• Add optional TPM security chip
• Improve signal routing for PCIe and USB
• Adjust USB ID pins from 3.3V to 1.8V
• Add optional resistors to allow USB Type-C power input

Revision E.1

Date: 2024-03-11

• Load Ethernet center tap capacitors for support of Ti DP83867 PHY on new revisions of GW70xx SOM modules

GW72xx Baseboard

Revision B.1

Date: 2021-04-29

• Initial release

Revision C

Date: 2021-08-29

• Improve passive PoE controller configuration
• Change R107 to a pull-down for PCIe spec compliance
• Swap UART4 and UART2 at the serial transceiver
• Improve power supply at 60V levels with capacitance
• Adjust passives for compliance on power supply
• Improve TVS diode
• Fix no connect on LAN7430 IC
• Improve silkscreen labels on PCB
• Rotate MIPI connector 180 degrees

Revision D

Date: 2022-02-22 (Preliminary)

• Add optional load resistors to pins 11 & 13 of Mini-PCIe slot J10 for optional modem compatibility
• Update TVS diode to bidirectional and move on connector side of reverse protection diode.
• Replace PCIe to GbE bridge LAN7430 to 88E8057 due to supply chain availability
• Update J5 & J11 silkscreen
• Add optional load resistors to route UART1 TX & RX to J5 as an alternative to Analog1 & 2
• Replace PoE diodes with different mechanical size due to supply chain availibility
• Do not load certain capacitors as per the RGMII Phy datasheet.
• Add optional load resistors for bypassing USB Hub and directing to Mini-PCIe slot J10

Revision E

Date: 2022-10-02

• Improve ESD protection for GPY111
• Add resistors for GND on mounting hole
• Add optional loaded resistors to J10 for swarm satellite

Revision F

Date: 2023-10-02

• Add 8-pin header (J28) for USB2.0/3.0 host (USB 3.0 Requires i.MX8M Plus SOM, GW702x)
  • Remove optional type A USB header option from the design (J18)
• Silkscreen improvements
• Add ESD protection for microSD/SIM, USB, Digital I/O, pushbutton, and user LED
• Add optional TPM
• Improve signal routing for PCIe and USB
• Add optional resistors for swapping UART4 TX & RX

Revision F.1

Date: 2024-03-11

• Load Ethernet center tap capacitors for support of Ti DP83867 PHY on new revisions of GW70xx SOM modules

Revision G

Date: 2024-04-19

• Replace obsolete U15 NCP1094 PoE controller with Ti TPS2378 PoE controller
• Replace obsolete U20 88E8057 Marvell PCIe GbE bridge with Microchip LAN7430 GbE bridge
• Change TPM reset input control from gpio to system reset by moving no load resistor from R209 to R208 in order to be compliant with the TCG specification
• Improve PoE isolation and current capacity
• Improve ESD immunity on board and OTG USB Port

GW73xx Baseboard

Revision B.1

Date: 2020-09-29

• Initial release

Revision B.2

Date: 2021-01-15

• Replace 3.2mm PEMs with 3.0mm

Revision C

Date: 2021-08-29

• Replace 4-port PCIe switch with 3-port. This removes PCIe routing to Mini-PCIe slot J10. Remove U3 multiplexer.
• Switch direction of D9 diode for testing protection
• Improve RJ45 LED brightness
• Improve PCIe capacitor values
• Add series capacitors to USBHUB_TXP2/TXN2 lines
• Use threaded holes for SOM and MIPI
• Upgrade RTC battery to rechargeable and remove GSC LDO
• Add pull-up line on USDHC2_RSTJ
• Improve power supply at 60V levels with capacitance
• Add TVS diode on power input for high voltage scenarios
• Add series resistor to POE PGOOD signal
• Improve D16 PoE Controller Diode for layout reasons
• Remove pull down resistor from WAD circuit
• Improve D7 diode for simplicity
• Improve PCIe signalling to 85ohm
• Improve trace length for SDIO ports

Revision C.1

Date: 2022-02-09

• Add resistor to resolve venice/errata#VN3PoECircuitLeakageResetVN3 PoE Errata
• Optimize RGMII Phy circuit per manufacturer recommendations by removing capacitors

Revision D

Date: 2022-08-23

• Replace LAN7430 with available 88E8057 Ethernet controller due to supply chain availability
• Improve ESD protection for GPY111 and PCIe Bridge
• Add optional loaded resistors to J10 for swarm satellite
• Improve 1.8V supply from 1A to 3A
• Do not load magnetic capacitors per the RGMII Phy datasheet.
• See Errata VN7 - New WiFi / BLE module on GW7301 from Laird Sterling LWB5 to 5+ is non operational. Note this module is not loaded on the GW7300 model.
• See Errata VN3 - Active PoE is non operational

Revision E

Date: 2023-02-02

• Resolve Errata VN7 & Errata VN3
• Improve ESD protection for microSD, SIM, USB ports, DIO, pushbutton switch, front panel LED

Revision F

Date: 2023-09-05

• Replace PCIe switch to support 3 Mini-PCIe slots
• Improve ESD protection for USB
• Resolve Venice errata VN3
• Add optional TPM
• Improve signal routing for PCIe and USB
• Add optional resistors for swapping UART4 TX & RX
• Improve AC coupling circuit for Mini-PCIe slots
• Add USB 3.0 & PCIe Multiplexer for slot J10

Revision F.1

Date: 2024-03-11

• Load Ethernet center tap capacitors for support of Ti DP83867 PHY on new revisions of GW70xx SOM modules

GW74xx Baseboard

Revision C

Date: 2023-08-25

• Initial release. For previous revision notes contact Gateworks support.

GW700x SoM

Revision A

Date: 2020-06-15

• Initial release

Revision B

Date: 2020-09-29

• Add power on status LED indicator
• Add JTAG_TRST# pull down resistor
• Replace JTAG connector with standard 10-pin connector used on other Gateworks product families

Revision C.1

Date: 2021-01-21

• Improve VDD_1P8 and VDD_5P0 power distribution
• Increase NVCC_DRAM supply current
• Adjust CPU POR_B pullup

Revision D

Date: 2021-03-01

• Increase 5V copper fill

Revision E

Date: 2021-12-01

• Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability (Requires software update described in Venice VN4 Errata)
• Added series protection resistors to JTAG serial port signals

Revision E.1

Date: 2022-03-14

• Improve new GPY111 PHY circuit per Venice VN5 Errata
• Improve transceiver driving JTAG UART circuit

Revision F

Date: 2022-03-28

• Roll changes in E.1 into PCB rather than rework

Revision G

Date: 2024-03-04

• Replace GPY111 PHY with TI DP83867 RGMII/SGMII GbE PHY
• Improve signal routing for ESD / EMI Improvements

Newport Family

GW610x

Revision B

Date: 01/10/2018

• Initial release

Revision B.1

Date: 08/02/2019

• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision C

Date: 2021-11-22

• Improve power supply protection for up to 60V DC input
• add GPS PPS option to pin 19 of J6 via resistor load
• Primary power supply regulation improvements

GW620x

Revision A.1

Date: 09/10/2018

• Initial release

Revision B

Date: 01/10/2018

• Disable USB Battery Charge Revision 1.2 (BC1.2) on Front Panel (USB BC disables USB power if a device does not negotiate within an amount of time which is too long for USB based modems to enumerate)
• Add 4.75K pull up resistors to all OcteonTX digital IO signals
• Fix CAN transceiver by terminating STBY signal to GND (see Errata NP7)
• Add build option to bypass the GSC battery LDO
• Add build option for LIS2DE12 3-axis accelerometer (loaded on GW6304)
• Add user pushbutton

Revision B.1

Date: 08/02/2019

• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision C

Date: 03/25/2020

• Add optional routing of GPS PPS signal to Mini-PCIe slot
• Improve resistor value for when GSC LDO is removed
• Add diode to barrel jack power input and remove diode in front of WAD circuit
• Improve silkscreen clarity of RJ45 PoE

Revision D

Date: 11/12/2021

• Improve reverse polarity power input circuit
• Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability. View Newport Errata NP12 & NP13.
• Added series protection resistors to JTAG serial port signals
• Improve high voltage circuit (60V continuous) protection
• Improve primary power supply current limit and signalling

Revision E

Date: 11/12/2022

• Improve RGMII/SGMII Phys
• Add ESD protection to RGMII/SGMII Phys

GW630x

Revision B.2

Date: 12/15/2017

• Initial release
• Fix GSC BATT current protection (cut/wire)

Revision B.3

Date: 01/04/2018

• Fix voltage strapping for MDIO (cut/wire) (see Errata NP1)
• Load resistors for PHY_RST# capability (see Errata NP1)

Revision C

Date: 01/04/2018

• Replace 0.22uF AC coupling caps on SerDes lanes with 0.1uF (recommended values for PCIe gen1/gen2)
• Move CPU LEDR from GPIO-13 to GPIO-31 to resolve CPU frequency strapping (850MHz -> 800MHz)
• Move PHY_RST# from GPIO-31 to GPIO-23 and make open-collector
• Fix voltage strapping for MDIO (see Errata NP1)
• Fix GSC BATT current protection
• Replace USB3 VBUS filters for improved manufacture-ability
• Add EMI protection on RJ45 LED's
• Added series resistor to miniPCI socket PERST# signals (to allow optional unload)

Revision D.1

Date: 01/13/2018

• Add reverse-polarity protection on Vin (see Errata NP2)
• Add external temperature sensor capable of providing CN80XX CPU die temperature (see Errata NP3)
• Add CN80XX FUSE blowing capability for chips supporting trusted boot (see Errata NP4)
• Use 0.22uF AC coupling caps for all PCIe channels as this is required for PCIe gen3 and backward compatible with gen1/2
• Improve FAN TACH circuit to support both open drain (OD) and driven TACH outputs
• Improve MMC trace routing
• Change boot device from eMMC_SS to the more robust eMMC_LS (which includes an eMMC reset before retry)
• Add CPU Speed adjustment capability using GSC (requires upcoming GSC feature)
• Add build option to allow off-board I2C to be at 5V or 3.3V
• Remove unnecessary SATA mux and replace AC coupling caps on PCIe RX differential pair going to J10 miniPCIe socket with 0ohm resistors. If user is going to be using an mSATA device on this socket they may need to have boards built with 0.1uf coupling caps here per the mSATA specification
• Add build option to allow isolating J11 miniPCIe clock signals to eliminate contention with non-standard cellular modems
• Add support for optional 802.3bt (PoE++)

Revision E

Date: 01/10/2018

• Disable USB Battery Charge Revision 1.2 (BC1.2) on Front Panel (USB BC disables USB power if a device does not negotiate within an amount of time which is too long for USB based modems to enumerate)
• Add 4.75K pull up resistors to all OcteonTX digital IO signals
• Fix CAN transceiver by terminating STBY signal to GND (see Errata NP7)
• Add build option to bypass the GSC battery LDO
• Add build option to support Unex V2X miniPCIe form-factor radio
• Add build option for LIS2DE12 3-axis accelerometer (loaded on GW6304)

Revision E.1

Date: 08/02/2019

• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision F

Date: 09/16/2021

• Add build option to route GPS PPS to J10.19 via resistor load
• Reduce leakage current when GSC LDO is unloaded via build option
• Add reverse polarity diode protection to avoid backfeed to barrel jack when powered via PoE
• Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability
• Improve feedback path and signalling for VDD_CORE supply

Revision F.1

Date: 03/25/2022

• Resolve Newport Errata NP12 & NP13 related to the new GPY111 Ethernet PHY

Revision G

Date: 07/12/2022

• Add TVS protection to JTAG serial port signals
• Improve reverse-polarity protection
• Resolve Newport Errata NP14 by adding ESD Protection to eth0 RGMII Ethernet

GW640x

Revision A.1

Date: 06/21/2018

• Initial release

Revision B

Date: 11/29/2018

• Replace 0.22uF AC coupling caps on SerDes lanes with 0.1uF (recommended values for PCIe gen1/gen2)
• Change boot device from eMMC_SS to the more robust eMMC_LS (which includes an eMMC reset before retry)
• Add CN80XX FUSE blowing capability for chips supporting trusted boot (see Errata NP4)
• Add external temperature sensor capable of providing CN80XX CPU die temperature (see Errata NP3)
• Add CPU Speed adjustment capability using GSC (requires upcoming GSC feature)
• Add build option to allow off-board I2C to be at 5V or 3.3V
• Remove unnecessary SATA mux and replace AC coupling caps on PCIe RX differential pair going to J10 miniPCIe socket with 0ohm resistors. If user is going to be using an mSATA device on this socket they may need to have boards built with 0.1uf coupling caps here per the mSATA specification
• Add build option to allow bypass of serial port transceiver
• Fix CAN transceiver OSC input
• Fix QSGMII SPD/ACT LEDs
• Add reverse-polarity protection on Vin (see Errata NP2)
• Add buid option to allow bypass of PoE circuit
• Improve FAN TACH circuit to support both open drain (OD) and driven TACH outputs
• Add support for optional 802.3bt (PoE++)
• Improve processor core voltage rail by widening copper fills
• Increase output voltage of GSC input LDO from 3.32V to 3.5V to avoid draining surface charge from newly installed battery
• Replace heatsink with fansink

Revision B.1

Date: 08/02/2019

• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision B.1 (GW6404 only)

Date: 11/29/2018

• Fix CAN transceiver by terminating STBY signal to GND (see Errata NP7)

Revision B.2 (GW6404 only)

Date: 04/19/2019

• Remove unused capacitor C21

Revision B.3 (GW6404 only)

Date: 08/02/2019

• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision C

Date: 02/28/2020

• Replace CAN Bus STBY no connect with ground
• Add 3-axis accelerometer (optional)
• Replace CFG_BC_EN 10K pull-down resistor with 200K to disable USB-IF R1.2 battery charging
• Add 4.75K pullup resistors to OcteonTX digital I/O signals that are available to the user on the GPIO connector
• Add zero ohm configuration resistors to connect LDO output to 3.3V for customers not using shut down and wanting to monitor the battery voltage.
• Route GPS PPS to pin 19 of J10 and J12 through a zero ohm resistor.

GW650x

Revision A

Date: 12/21/2021

• Initial release
• Based on the GW6400-C with the following changes:
  • Reduce leakage current when GSC LDO is unloaded via build option
  • Add diode to barrel jack power input and remove diode in front of WAD circuit
  • Add heat sink mounting holes near CPU
  • Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability
  • Replace clock generator with new generator and crystals due to part availability
  • Improve feedback path and signalling for VDD_CORE supply
  • Replace Quad SGMII PHY with a variant that does not support SFP Fiber due to part availability (remove SFP/Fiber from design)
  • Replace combo microSD/SIM socket with individual microSD and nanoSIM

Revision A.1

Date: 02/09/2022

• Resolve Newport Errata NP12 & NP13 related to the new GPY111 Ethernet PHY

Revision B

Date: 09/09/2022

• Correct Ethernet LEDs
• Add TVS protection to JTAG serial port signals
• Improve reverse-polarity protection
• Resolve Newport Errata NP14 by adding ESD Protection to eth0 RGMII Ethernet
• Improve current for power supplies
• Correct layout for .9V rail

Revision C

Date: 10/13/2022

• Bypass USB hub which removes USB signalling from Mini-PCIe sites J9 & J11 and front panel top USB jack.
• Add ESD protection to the microSD, status LED, pushbutton switch, USB 3.0 front panel connector and 4x gigabit connectors
• Add optional resistors to Mini-PCIe J12 pins 6, 28 and 48 for modems, example given Telit LE910C4 modem compatibility

Revision D

Date: 01/02/2023

• Add resistors to enable power for USB when hub is unloaded

GW6903

Revision B.1

Date: 03/30/2020

• Initial release

Revision C

Date: 10/12/2020

• Improve resistor value for when GSC LDO is removed
• Connect D2 Red LED anode to 3.3V instead of 5V
• Connect CPU USB power pins J20 and K20 to 3.3V

Revision C.1

Date: 12/12/2020

• Add resistor to R4 to bring resistance to 151 ohm to make red LED more bright

Revision C.2

Date: 12/16/2020

• Update R4 resistance to 150 ohm to make red LED more bright

Revision C.2

Date: 12/16/2020

• Update R4 resistance to 150 ohm to make red LED more bright

Revision D

Date: 11/19/2021

• Improve 60V continuous input voltage operation
• Improve primary power supply conditioning
• Improve spike protection for large output transients at high input voltage
• Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability
• Improve LED brightness
• Added series protection resistors to JTAG serial port signals

Revision E

Date: 07/05/2022

• Improve ESD protection to the GPY111 Phy

---

Ventana Family

GW51xx

Revision A

Date: 04/19/2013

• Initial release

Revision B

Date: 09/17/2013

• Add VDD_HIGH to GSC analog input for voltage monitoring
• Select GPS 4800 baud NMEA protocol by default
• Reduce voltage drop for USB OTG VBUS
• Adjust 5V boost converter feedback resistors for more accurate 5V
• Add i.MX6 GPIO control of mini-PCIe WiFi? disable
• Move mounting holes to match other Ventana boards
• Improve HDMI and OTG connectors footprints
• Modify JTAG route from a star to a daisy chain topology

Revision B.1

Date: 11/08/2013

• Eliminate possible high input voltage on the switching supply enable input by removing unnecessary R34 pullup

Revision C

Date: 09/04/2014

• Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
• Connect GPS PPS signal to reserved pin 49 on Mini-PCIe socket through unloaded configuration resistor
• Change GSC VDD_HIGH connection to include a divide-by-two resistive divider since voltage exceeds analog-to-digital converter 2.5V reference
• Add GSC analog input option to DIO
• Replace U15 input power supply to increase operating voltage range and improved manufacturability
• Ground RTC XTAL input to eliminate noise causing pre-mature watchdog resets (see Errata HW7)

Revision D

Date: 03/05/2015

• Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
• Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
• Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
• Reduce PORJ pullup resistor value for faster rise time Improve inductor footprints for improved manufacturability

Revision E.1

Date: 12/23/2015

• Add series resistor between battery positive and reverse current diode for UL two level protection
• Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
• Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input

Revision F

Date: 10/17/2016:

• Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
• Replaced GbE crystal for increased lifespan

Revision F.1 (GW5104 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

GW520x

Revision A

Date: 10/18/2013

• Initial Release

Revision A.1

Date: 10/18/2013

• Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance.

Revision B.1

Date: 1/30/2014

• Add WiFi disable signal to all Mini-PCIe sockets through zero ohm resistors
• Add optional load JST 1x2x2mm connector under the pushbutton switch
• Add ability to route USB OTG to miniPCIe socket instead of front-panel via GPIO
• Replace 2-pin tamper switch connector with 3-pin connector to support CAN Bus, RS485, TTL serial and tamper switch option
• Add optional CAN Bus transceiver
• Add optional RS485 transceiver
• Add optional TTL serial bypass resistors
• Add option for 3.3V and 5V power to one pin of the digital I/O connector through unloaded configuration resistors

Revision C.1

Date: 3/31/2015

• Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
• Replace 3.3V TVS arrays with 2.5V arrays for improved protection
• Add 3.3V voltage translator to both 2.5V PCISKTx_RSTJ signals for increased voltage margin
• Remove capacitor on tamper switch input to reduce switch debounce time constant
• Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in
• Connect I2C3 bus to the digital I/O connector through unloaded configuration resistors
• Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets through unloaded configuration resistors
• Add changes to support SOM application, (a) add CAN bus transceiver bypass resistors, (b) add RS232 transceiver bypass resistors, (c) add connector under uSD/SIM socket to support SD, USB, battery voltage, and reset, (d) add 2-pin power input connector
• Add "USB" to PCIe socket silkscreen for clarification

Revision C.2

Date: 4/3/2015

• Add 100 ohm differential PCIe clock termination resistor for improved PCIe clock compliance.

Revision D

Date: 2/18/2016

• Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
• Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
• Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J11.5 as an option
• Add optional GSC analog input to J4.1 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
• Add optional 4-pin friction latching connector for micro-B OTG connector
• Add optional OTG ID pulldown resistor to configure OTG port for host operation when optional 4-pin connector is loaded
• Reduce PORJ pullup resistor value for faster rise time
• Add series resistor between battery positive and reverse current diode for UL two level protection
• Add processor watchdog support by connecting WDOG_B to PMIC PWRON input
• Add support for UHS-1 MMC cards to run at their full speed capability
• Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input
• Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
• Update SIM/uSD socket footprint and move 0.2mm closer to board edge for improved manufacturing
• Move USB signals away from SIM/uSD mounting tab slot to improve fabrication processes

Revision D.1 (GW5204 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

Revision E

Date: 5/13/2020:

• Add GSC input LDO for battery powered applications with ability to bypass
• Swap RTS and CTS at the input to the U12 serial transceiver since i.MX6 defines opposite to the RS232 standard
• Add PERST# optional load series resistors for Sierra Wireless Modem consistency
• Add 1k pulldown resistor on the output of the PERST# voltage translation buffer to improve power sequencing
• Remove PCIe Receive Data capacitors
• Replace Sata recieve data 0.01uF with 0.1uF capacitors
• Connect GSC analog input to the video connector via series resistor for consistency to other members of Ventana family
• Add isolation resistors to PCIe clock, transmit and receive pairs on the Mini-PCIe socket with SIM signaling for non standard modems

GW522x

Revision A

Date: 01/29/2015

• Initial release

Revision A.1

Date: 04/21/2015

• Improve PCIe clock termination

Revision B

Date: 04/29/2015

• Reduce PORJ pullup resistor value for faster rise time
• Improve PCIe clock termination
• Add processor watchdog support by connecting WDOG_B to PMIC PWRON input (see [Errata HW12)
• Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)
• Correct the SPI connector bottom side silkscreen pin labels

Revision C

Date: 07/22/2015

• Add series resistor between battery positive and reverse current diode for UL two level protection
• Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see Errata HW14)
• Replace RGMII_TXCLK series resistor with 22.1 ohm device and add second 22.1 series resistor to RGMII_RXCLK to reduce radiated emissions
• Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills

Revision D

Date: 01/04/2017:

• Add wide range linear regulator for powering the GSC battery from the input voltage when board power is turned off to extend battery life
• Add option for external GSC battery connector
• Replaced GbE crystal for increased lifespan

Revision D.1

Date: 01/06/2017:

• Add LDO output capacitor.

Revision E

Date: 05/16/2017:

• Swap CTS and RTS for optional UART flow-control (resistor option)
• Add series resistor on each miniPCIe PERST# signal to allow unloading if needed
• Add LDO output capacitor missing on Rev D and added on Rev D.1
• Replace LDO input capacitor with 100V variant for improved Vin margin
• Extend SPI from J24 connector to J8 via optional series resistors

Revision F

Date: 11/29/2018:

• added build option for alternate 2-pin power input

Revision F.1 (GW5224 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

GW53xx

Revision A

Date: 12/17/2013

• Initial revision

Revision A.1

Date: 12/17/2013

• Replace decoupling capacitors on the clock buffer input with series resistors for improved PCIe clock performance

Revision B

Date: 12/05/2013

• Add resistor load option for I2C support via DIO connector

Revision C

Date: 07/29/2015

• Replace obsolete J2 uSD/SIM socket with functionally equivalent socket
• Improved RJ45 TVS arrays
• Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
• Remove capacitor on tamper switch input to reduce switch debounce time constant (see Errata HW4)
• Add Schottky diode to USB_H1_VBUS net to prevent i.MX6 backfeed when board is powered off and active USB cable is plugged in (see Errata HW8)
• Connect GPS PPS signal to reserved pin on both Mini-PCIe sockets pin 49 through unloaded configuration resistors
• Add optional GSC analog input to J10.4 connector through divide by two configuration resistors unloading the series resistor for backwards compatibility
• Increase USB boost converter power to 1.6A max current (see Errata HW6)

Revision C.1

• Update GW53xx-C to increase current capacity of SOC Voltage rail

Revision C.2

• Update GW53xx-C to include 100 ohm differential PCIe clock termination resistor.

Revision D

Date: 10/10/2014

• Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
• Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
• Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default and audio connector as an option
• Add option to bypass CAN bus transceiver to provide additional TTL UARt
• Add option to bypass RS232 transceiver

Revision E

Date: 03/31/2015

• Reduce PORJ pullup resistor value for faster rise time
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
• Reduce PCIe clock jitter to GEN2 levels by replacing clock buffer with clock generator and connecting clock output back to processor PCIe clock input (see Errata HW14)
• Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
• Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)

Revision F

• Improve 5V Boost Supply for powering CAN, HDMI, and LVDS. (resolves Errata HW18)
• Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
• Improve voltage rails with larger traces and capacitors for greater stability when operating in LDO-Bypass mode
• Improve USB host connector durability

Revision F.1 (GW5304 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

Revision G

Date: 9/23/2019:

• Replace EOL Wi2Wi GPS receiver with ublox ZOE-M8Q
• Replace EOL 88E1510 RGMII phy (eth0) with DP83867 phy
• Replace EOL ADV7180 with ADV7280A analog video decoder
• Replace EOL HDMI termination with updated version
• Replace EOL 88E8057 MAC/PHY (eth1) with Intel I210 MAC/PHY
• Add GSC input LDO for battery powered applications
• Add full-deplex bridge rectification for eth0/eth1 PoE for full 802.3af compatibility
• Replace input voltage reverse protection diode with Mosfet to improve efficiency at higher input currents
• Add 1K pull-down resistors to the miniPCIe and GbE controller reset outputs
• Add normally-loaded zero ohm resistor on J6 miniPCIe socket clock, TX and RX data pairs to allow isolation for non-compliant cards
• Add normally-loaded zero ohm resistor on all miniPCIe PERST# signals to allow isolation for non-compliant cards
• Add normally enabled power switch to gate 3.3V rail to J6 miniPCIe socket to allow software power control
• Remove un-necessary J9 PCIe RX capacitance
• Replace SATA RX 0.01uF AC coupling capacitor with a 0.1uF device for specification compliance

This revision does require software updates detailed in Ventana Errata 22-26.

Revision G.1

Date: 5/27/2020:

• Update MAC address programming for eth1 (see Ventana Errata 28).

GW54xx

Revision B

Date: 03/14/2013

• Initial Revision

Revision C

Date: 07/16/2013

• Add optional 3.3V primary power supply bypass connector to power the board with well regulated 3.3V +/-5% input
• Fix Analog Video input functionality (see Errata HW1)
• Fix GPS Antenna Short Protection (see Errata HW2)
• Replace MMA8451 accelerometer with FXOS8700 accelerometer/magnetometer
• Replace GPS with Wi2Wi Wi2Wi W2SG0008i for improved functionality
• Replace UART handshake with additional UART tx/rx and made previous hardware handshaking a resistor loading option

Revision D

Date: 01/13/2014

• Add optional serial console bypass to the RS485 connector
• Add PoE diodes to second Ethernet connector for increased functionality
• Add i.MX6 GPIO control of mini-PCIe WiFi? disable
• Add installed SIM card outline to silkscreen for ease of use

Revision E

Date: 6/28/2016:

• Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
• Connect GPS PPS signal to reserved pin 49 of J9 (Top right) and J10 (Bottomr left/center) Mini-PCIe sockets through unloaded configuration resistors as a build option
• Add 3.3V voltage translator to miniPCIe socket PERST# signals for increased voltage margin
• Unload capacitor C473 to resolve issue with off-board tamper signal (see Errata HW4)
• Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
• Add ability to bypass CAN transceiver through loadable resistors
• Add ability to bypass UART2 RS232 transceiver through loadable resistors
• Improved GPS Antenna short circuit fault monitoring by lowering trip threshold to allow for higher power active antennas
• Replace audio codec logic ground connection with two zero ohm configuration resistors for connecting to analog ground by default audio connector J28.5 as an option
• Add 0 to 5V GSC analog input available via 3-byte register at 0x1A to previously unused J27.4 connector
• Add resistor loading option to provide 3.3V to J16.3
• Add resistor loading option to provide 5.0V to J16.4
• Add series resistor between battery positive and reverse current diode for UL two level protection
• Add processor watchdog support by connecting WDOG2_B to PMIC PWRON input (see Errata HW12)
• Reduce PCIe clock jitter to GEN2 levels by routing clock generator output back to processor PCIe clock input (see Errata HW14)
• Add support for UHS-1 MMC cards to run at their full speed capability (see Errata HW16)
• Add a reset generator to improve signalling during board reset
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills for greater stability when operating in LDO-Bypass mode as well as supporting higher frequency processors
• Reduce emissions / EMI on RGMII clock signal with 22 ohm series resistor
• Improve USB host connector durability
• Add SPI support via J32 ((ECSPI2 SS0) (see SPI))

Revision E.1

Date: 6/29/2016:

• Increase VDD_1P8 current flow with soldered wire

Revision F

Date: 11/01/2016:

• Increase VDD_1P8 trace width to remove need for wire from Revision E.1

Revision F.1 (GW5404 only)

Date: 1/13/2019:

• Change resistor loading for PCIe routing to mezzanine connector. Read more here

Revision F.2 (GW5404 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more Ventana HW22

Revision G.1

Date: 9/23/2019:

• Replace EOL Wi2Wi GPS receiver with ublox ZOE-M8Q
• Replace EOL 88E1510 RGMII phy (eth0) with DP83867 phy
• Replace EOL ADV7180 with ADV7280A analog video decoder
• Replace EOL HDMI termination with updated version
• Replace EOL 88E8057 MAC/PHY (eth1) with Intel I210 MAC/PHY
• Add GSC input LDO for battery powered applications
• Add full-deplex bridge rectification for eth0/eth1 PoE for full 802.3af compatibility
• Replace input voltage reverse protection diode with Mosfet to improve efficiency at higher input currents
• Add 1K pull-down resistors to the miniPCIe and GbE controller reset outputs
• Add normally-loaded zero ohm resistor on J7 miniPCIe socket clock, TX and RX data pairs to allow isolation for non-compliant cards
• Add normally-loaded zero ohm resistor on all miniPCIe PERST# signals to allow isolation for non-compliant cards
• Add normally enabled power switch to gate 3.3V rail to J7 miniPCIe socket to allow software power control
• Remove un-necessary J11 PCIe TX capacitance
• Replace SATA RX 0.01uF AC coupling capacitor with a 0.1uF device for specification compliance

This revision does require software updates detailed in Ventana Errata 22-26.

Revision G.2

Date: 5/27/2020:

• Update MAC address programming for eth1 (see Ventana Errata 28)

Revision H

Date: 7/21/2020:

• Improve power management integrated circuit (see Ventana Errata 29)
• Add optional resistor load to route UART5 through the RS232 Transceiver

GW551x

Revision A.1

Date: 01/08/2015

• Initial release

Revision B

Date: 02/18/2015

• Move passives further from mounting holes
• Increase spacing between the HDMI input and HDMI output connectors
• Reduce PORJ pullup resistor value for faster rise time
• Improve HDMI video input to allow YUV422 semi-planar input allowing 1080p@60Hz (see Errata HW9)
• Fix USB OTG device mode (see Errata HW10)

Revision C

Date: 10/06/2016:

• Add series resistor between battery positive and reverse current diode for UL two level protection
• Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input (see Errata HW12)
• Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
• Adjust processor drive on CPU crystal for increased lifespan
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills

Revision C.1

Date: 02/10/2017:

• Fix HS/CLK on HDMI Input

Revision D

Date: 03/02/2017:

• Fix YUV422 semi-planar HDMI input to support 1080p60

Revision D.1 (GW5514 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

GW552x

Revision A.2

Date: 11/19/2014

• Initial release

Revision B

Date: 07/29/2015

• Add diode to prevent power backfeed when board is powered off and a USB cable is plugged in to a powered host (see Errata HW8)
• Add 3.3V voltage translator to 2.5V PCISKTx_RSTJ signals for increased voltage margin
• Move watchdog timer from WDOG2_B to WDOG1_B for mainstream Linux support
• Add 32.768KHz crystal to processor real time clock for increased watchdog timer and Linux time of day accuracy
• Move barrel jack to the opposite side of the power supply to eliminate interface between HDMI and barrel jack mating connectors
• Add software controllable USB switch to configure one of the panel USB ports for either host or device

Revision C

Date: 03/29/2016

• Reduce PORJ pullup resistor value for faster rise time
• Add series resistor between battery positive and reverse current diode for UL two level protection
• Adjust processor drive on CPU crystal for increased lifespan
• Improve processor core voltage rails by adding on 22uF capacitor to both VDD_ARM and VDD_SOC and widening copper fills
• Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
• Reduce PCIe clock jitter to GEN2 levels by adding a clock generator providing the CPU and PCIe socket clock input (see Errata HW14)
• Add resistor load option for SPI support via J8 ((ECSPI3 J8.1:SS0# J8.2:SCLK, J8.17:MOSI, J8.18:MISO see SPI))
• Add resistor load option for I2C support via J8 ((I2C3: J8.17:SCL, J8.18:SDA))
• Move battery to reduce heat impact on it's lifespan
• Replace J8 10pin connector with 20pin connector

Revision C.1

Date: 10/18/2016

• Replace J8 20pin connector with 10pin connector (20pin connector available as option)

Revision D

Date: 01/01/2020

• Connect USB_OTG_VBUS to 5V for supporting device mode
• Add a series resistor on the PCIe reset signal of each Mini-PCIe socket to support certain modems which use this pin for another purpose
• Add a 1K pull down resistor to the output of the PCIe reset voltage translation buffer

GW553x

Revision B

Date: 08/30/2016

• Add processor external watchdog support by connecting WDOG_B to PMIC PWRON input
• Replace 2-pin connector with reset switch for standard product (2-pin connector is optional)
• Replace 2-pin connector with user LED (2-pin connector is optional)

Revision B.1 (GW5534 only)

Date: 1/13/2019:

• Replace NAND flash. Has different block size. Read more here

GW5913

Revision A.1

Date: 7/2019

• Initial Release

Revision B

Date: 9/2019

• Remove Pull up resistor on GSC_WAKE signal on the GSC and attach PORJ to the pin instead
• Move MX6_DIO6 to GPIO_19 for 1588 support.
• Improve layout

Revision C

Date: 5/2021

• Add option for surface mount ethernet header
• Replace GSC crystal and crystal load capacitors to optimize oscillator operation and increase RTC accuracy

Revision D

Date: 12/2021

• Replace TI DP83867 RGMII/SGMII GbE PHY's with GPY111 due to part availability, see HW33
• Added series protection resistors to JTAG serial port signals

Revision D.1

Date: 6/2022

• Improve new GPY111 PHY circuit per Ventana HW34 Errata

Revision E

Date: 8/2022

• Improve new GPY111 PHY ESD per Ventana HW35 Errata

GW5910

Revision B

Date: 8/2019

• Initial Release
• Added TI CC1352P (not loaded on standard product)
  • Loaded on GW5910-SP414

Revision C

Date: 10/2019

• Update GSC crystal to eliminate oscillator faults

Revision D

Date: 1/2021

• Add optional GPS PPS signal routing
• Improve resistor value for when GSC LDO is removed
• Use different RS232 Transceiver
• Optimize Sub-1GHz CC1352 layout

---

Laguna Family

GW2388-4

Revision A

Date: 12/2009

• Initial Release

Revision B

Date: 05/2010

• Improve GSC battery circuit to increase battery life
• Add core buck regulator power sequencing for reliable power up
• Add VTT generator capacitance to reduce output ripple
• Correct SATA connector footprint and adding optional SATA power connector
• Replace through hole DB9 connector with surface-mount connector for improved manufacturing

Revision C

Date: 12/2010

• Change watchdog timer circuit to ensure narrow pulse width generates reset
• Add ARM processor digital I/O control of USB voltage generator
• Add GW16038 mounting hole for increased mechanical retention
• Add fifth GW2388 mounting hole near center of board for increased stability in high vibration environment
• Add support for micro SD card detection signal
• Add optional USB header under USB panel jack for optional external connector mounting
• Add series resistor to the GPS receiver antenna power signal to remove possibility of circuit damage in response to an antenna short
• Add filter capacitors to LED, reset, and tamper switch connectors to reduce radiated emissions.

Revision D

Date: 09/2011

• Increase default DDR2 memory size from 128Mytes to 256Mbytes due to price reduction in newer parts
• Replace core voltage switchers with newer devices that do not require the reset generator for under voltage lockout
• Update primary 3.3V switcher with newer Mosfets and Inductor to improve efficiency by 10% and improve transient response for supporting higher power radios.

Revision E

Date: 08/2012

• Change the Mini-PCIe bridge reset from system reset to ARM Processor GPIOA11 to ensure it remains low until after the PCIe clock is valid.

Revision F

Date: 12/2012

• Terminate unused PCIe bridge inputs to correct for TI design flaw that potentially locks up the bridge at low temperature and high humidity environments
• Replace bipolar transistor used to drive fan with a MOSFET device for increased current capability
• Add passive filter to JTAG system reset input to reduce EMI sensitivity.

Revision G

Date: 12/2013

• Replace ARM processor clock with an external clock generator to reduce jitter on PCIe differential clocks
• Add diodes to the PoE return paths on both channels for full isolation when being powered by an 802.3 switch
• Replace N-channel MOSFET used to drive fan with a P-channel device for proper control.

Revision H

Date: 02/2014

• Move the PCIe interrupts from processor digital I/O signals to dedicated interrupts for improved interrupt capability

Other SBC Families

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