Changes between Version 4 and Version 5 of venice/edgelock

Timestamp:

03/11/2026 06:51:30 PM (4 days ago)

Author:

Ryan Erb

Comment:

add edgelock vs tpm

venice/edgelock

@@ -28 +28 @@
 ||= Family =||= Board =||= Chip =||= bus/address =||= reset =||
 || VeniceFLEX   || GW8201-C+ || SE052F || I2C2@0x48 || N/A ||
+|| Catalina   || GW9xxx || SE052F || I2C2@0x48 || N/A ||
 
 * Note, the SE052F is not available on standard Venice, only VeniceFLEX
 
+==== Edgelock vs TPM
+
+In many high-end embedded designs, engineers will actually use both—the TPM to secure the Linux operating system, and the Secure Element to handle the application's connection to the outside world (cloud).
+
+The TPM used on the Gateworks SBC (see wiki:tpm ) is great for making sure your Gateworks board only boots if the firmware hasn't been tampered with (secure boot). 
+
+|| '''Feature''' || '''NXP SE052F (Secure Element)''' || '''Microchip ATTPM20P (TPM 2.0)''' ||
+|| '''Primary Function''' || Device-to-cloud authentication, credential vault || OS Root of Trust, Secure Boot, Platform Configuration Registers ||
+|| '''Architecture''' || Javacard OS running NXP IoT Applets || TCG TPM 2.0 Compliant ||
+|| '''Primary Interface''' || I2C & Contactless || SPI ||
+|| '''Max RSA Support''' || Up to 4096-bit || Up to 2048-bit ||
+|| '''Max ECC Support''' || Up to 521-bit || Up to 256-bit ||
+|| '''Hashing Algorithms''' || SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 || SHA-1, SHA-256 ||
+|| '''User Memory''' || 100 KB secure flash || 16 KB non-volatile memory ||
+|| '''Certifications''' || FIPS 140-3 Level 3, Common Criteria EAL 6+ || FIPS-140-2 compliant DRBG ||
+|| '''Primary Use Case''' || IoT cloud connections, custom applets || Linux measured boot, secure boot, LUKS disk encryption ||
+
+See also (see wiki:tpm )
 
 == Software