wiki:venice/errata

Version 4 (modified by Tim Harvey, 3 years ago) ( diff )

added GPY111 PHY errata

Venice Errata

The below errata only affects certain models and certain revisions.

Please contact support@… with any questions.

VN1 eth0 LED's dim

Issue:

  • The Link speed and activity LED's on the eth0 RJ45 are insufficiently illuminated.

Resolution:

  • This is resolved on PCB 02210198-02 (GW730x-C) (Rev C)

Affected Product:

  • GW730x-B (PCB 02210198-01)

VN2: GSC lockup

Issue:

  • An errata in the MSP430FR5847 used as the GSC (GSCv3) for Venice single board computers can cause unexpected GSC lockup events. The effects of a GSC lockup can be described as:
    • failure of board to boot due to inability to read board I2C EEPROM
    • failure to read the I2C RTC and update the system time
    • failure to adjust ARM CPU core voltage regulator during cpu frequency changes
    • loss of RTC and GSC register configuration

Affected Product:

  • GW7xxx

Resolution:

  • Update boards to GSC firmware v60

Fixed in:

  • GSC firmware v60

VN3 PoE Circuit Leakage & Reset

Issue:

  • PoE leakage current can charge up the barrel jack detection circuit (WAD circuit) and shut down the PoE input
    • Add resistor to sink current

Affected Product:

  • GW730x-C (PCB 02210198-02)
  • GW7902x-C (PCB 02210224-02)

Resolution:

  • This is resolved on PCB 02210198-02 (GW730x-C.1) (Rev C.1)
  • This is resolved on PCB 02210224-02 (GW7902-C.1, SP467-C.2 & C.3, SP476-C.1, SP477-C.1, SP481-C.1 ) (Rev C.1)

VN4 GPY111 PHY replacement

Issue:

  • Due to supply chain limitations the DP83867 GbE PHY has been replaced with the GPY111 GbE PHY

Resolution:

Affected Products:

  • GW700x-E+ (PCB 02210210-04) (SoM used on GW710x/GW720x/GW730x boards)
  • GW7902-C+ (PCB 02210224-02)

Notes:

  • To determine what version of SoM your GW710x/GW720x/GW730x board uses use the 'gsc' command in U-Boot:
    u-boot=> gsc
    Model   : GW7300-00-B1B
    Serial  : 852418
    MFGDate : 10-20-2020
    SOM     : GW7000-B 852418 10-20-2020
    BASE    : GW7300-B1 849162 10-06-2020
    ...
    
  • If your software has the required support the PHY will be shown in U-Boot as follows:
    Net:   GPY111 eth0: ethernet@30be0000 [PRIME]
    

VN5 GPY111 PHY bit error rate and link errata

Issue:

  • The GPY111 PHY used on a variety of boards in the Venice product family has some errata from the manufacturer that affects Venice products:
    1. When operating on a GbE link occasionally a link will have a high CRC error rate directly after a cable plug-in or board power-up event. A link down/up event will typically resolve this issue.

Resolution:

  • Issue #1 is addressed internally by firmware in the PHY: If the PHY exceeds an allowed threshold of 'Start-of-Stream Delimiter' (SSD) errors it will restart link negotiation a number of times before finally giving up and will then 'Auto-Downspeed' (ADS) to a 100mbps link. This feature is configured by the PHY LSADS field (bit 15 - 14) of the PHY_PHYCTL2 MII register (0x14) where a value of 00b is Off (ADS disabled), 01B will retry 1 time, 10B will retry 3 times (default), and 11B will retry 4 times. An ADS event is signaled by the LSADS bit (bit 8) of the PHY_PHYSTAT1 (0x11) MII register being set. The overall affect of using ADS is that the link may not be stable until it has settled after the link is brought up and in rare cases the link may settle at 100mbps. In extensive testing it has been found that link retries occurs about 1 in 100 plug-in/power-up events, an Auto-Downspeed to 100m occurs less than 1 in 5000 plug-in/power-up events, and that the link is stable within 30 seconds.

Affected Products:

  • GW700x-E+ (PCB 02210210-04)
  • GW7902-C+
  • GW7903-A+
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