Changes between Version 20 and Version 21 of venice/npu


Ignore:
Timestamp:
09/10/2024 09:44:12 PM (2 months ago)
Author:
Ryan Erbstoesser
Comment:

add links to tpu page

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  • venice/npu

    v20 v21  
    66 * All GW74xx use the i.MX8M Plus processor
    77 * Any GW71xx, GW72xx and GW73xx using a GW702x SOM module will use the i.MX8M Plus processor
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     9Please note other AI accelerators can also be added via expansion slots described [wiki:TPU here]
    810
    911The IMX8MP NPU IP is !VeriSilicon (Vivante VIP8000) and offers 2.3 TOPS of acceleration for inference in endpoint devices; object identification, speech recognition of 40K words, or even medical imaging (!MobileNet v1 at 500 images per second). Out of the box, this makes Gateworks boards with NPU capabilities powerful for AI applications on the edge.
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     356== Other AI Chipsets and Solutions
     357
     358Please note other AI accelerators can also be added via expansion slots described [wiki:TPU here]
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