Changes between Version 81 and Version 82 of gsc

Timestamp:

07/22/2021 07:45:10 PM (3 years ago)

Author:

Cale Collins

Comment:

added note that driver will clear interupt bits

gsc

@@ -122 +122 @@
 [=#gsc_interrupt_status]
 === GSC_INTERRUPT_STATUS (Register R10): Interrupt Source
-The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.
+The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.  
+
+** Note: These bits will be cleared automaticly by the driver **
 
 ||= Bit =||= Name =||= Description =||