Also see the Gateworks generic PCI wiki page: PCI
Venice IMX8M PCIe Support
The IMX8MM SoC has a single PCIe Gen 2 host controller and the IMX8MP SoC has a single PCIe Gen 3 host controller. Many Venice models have an on-board PCIe switch which allows the board to support more than 1 PCIe endpoint device. Note that the GW72xx/GW73xx/GW74xx boards have a Gen2 PCIe switch so even if you have one of those boards with a Gen3 capable PCIe host controller you will not have Gen3 from host to endpoint. This is not the case with Venice-Flex which uses an IMX8MP along with GW82xx/GW92xx baseboards for a Gen3 link from host to endpoint.
A PCIe switch operates like a PCI bridge such that it will create additional subordinate busses.
Some Mini-PCIe slots only have USB signalling and not PCIe signalling, with cellular modems in mind.
Special Notes
- The GW82xx Venice-Flex baseboard has a Gen 3 PCIe switch therefore can support host to endpoint Gen 3 PCIe performance.
- The GW74xx SBC uses a i.MX8M Plus CPU which supports Gen 3 PCIe, but the PCIe switch used on GW74xx is Gen 2.
- When using a GW702x i.MX8M Plus SOM which supports Gen 3 PCIe with a GW72xx/GW73xx baseboard, the switches used on the baseboard are Gen 2. GW71xx does not have a switch and thus can support Gen 3.
- Venice GW82xx (PCIe Gen3) has around a 1.5x performance increase on PCIe throughput relative to the GW72xx (PCIe Gen2). This is inline with the Gen2 vs Gen3 speeds.
PCIe Pinout
Please see the user manual for the specific board model following the links here
1.5V Rail
While 1.5V is on the Mini-PCIe specification, Gateworks does not bring this voltage out to the slots. Some obscure Mini-PCIe cards may use this voltage and thus may not work properly in the Gateworks slot.
PCIe Throughput
There are several factors that can affect PCIe performance. The most obvious factor is how many lanes (pairs of TX/RX SERDES channels) you have: 1x, 2x, 3x, 4x etc which are pure multipliers to the rates that can be achieved over a single lane. The next most obvious factor is what generation of PCIe your host controller (root complex or RC) and device (endpoint or EP) supports: Gen1, Gen2, Gen3 etc which factors into the transfer rate and data transfer overhead [1]. Digging deeper into the Transaction Layer Packet (TLP) overhead is not as obvious as RC's and EP's have varying max payload packet sizes. Digging even deeper than this you will get to specific limitations within the i.MX8M PCIe host controller.
The i.MX8M PCIe host controller has a limit where if the data transfer size exceeds 400 Bytes, the number of inbound MWr TLP transactions that the controller can support is up to the combination of 12 headers and 400 bytes of data payload as long as neither is exceeded. Higher performance can be obtained by having hte i.MX8M host controller issue outbound MRd transactions instead of using inbound MWr. See AN13164 iMX8MP PCIe Bandwidth Analysis.
PCIe Reset
Reset signals are routed to the Mini-PCIe sockets. On boards without a switch this is an i.MX8M GPIO and on boards with a PCIe switch an i.MX8M GPIO drives the PERST# of the switch and the switch automatically controls the PERST# signal going to each down-stream socket and they can not be independently controlled.
PCIe / USB3 Mux
Mini-PCIe cannot support USB 3.0 and PCIe at the same time, thus the mux is used to choose which to use.
Note USB 3.0 is only available on Venice with a SOM module that supports USB 3.0.
- GW7300-F and newer have a PCIe and USB 3.0 mux for Mini-PCIe slot J10.
- GW7200-F and newer have a PCIe and USB 3.0 mux for Mini-PCIe slot J10.
- GW7100 has a PCIe and USB 3.0 mux for Mini-PCIe slot J6.
This mux is controlled through GPIO1_6 (default 0, which is PCIe), with a bootloader example shown below: (adjust per board, focus on gpio named pci_usb_sel)
u-boot=> gpio status Bank GPIO1_: GPIO1_0: output: 0 [x] rs485_term.gpio-hog GPIO1_1: input: 0 [x] mipi_gpio4.gpio-hog GPIO1_6: output: 0 [x] pci_usb_sel.gpio-hog
To set this GPIO high (USB 3.0) in uboot:
gpio set GPIO1_6
To clear this GPIO high (PCIe) in uboot:
gpio clear GPIO1_6
Then boot the board via the boot command:
boot
It is recommended to adjust this GPIO in the bootloader and not when the board boots into Linux. If the GPIO state does not persist across reboots, then add the command to the extra variable.
MSI Notes
Some devices/drivers require MSI interrupts and some require legacy interrupts (ath9k radio devices come to mind which require legacy interrupts).
MSI allows up to 32 interrupts where-as MSI-X allows up to 2048 interrupts. Note however that the IMX8M SoC's only support MSI - if a device supports MSI-X the interrupts will fall-back to MSI.
The Designware PCIe core (used on IMX6/IMX8M) works as such as soon as any MSI interrupt is enabled, the core no longer forwards legacy IRQs so if any card in your system needs legacy interrupts you need to disable MSI with pci=nomsi in uboot:
setenv extra 'pci=nomsi' saveenv reset
If you have a PCIe card that requires legacy interrupts you can use 'pci=nomsi' but this means you will not be able to use any card that 'requires' MSI (ath11k radio devices come to mind). Enable it if you need to to make your system work.
