|Version 1 (modified by 19 months ago) ( diff ),|
Venice IMX8M PCIe Support
The IMX8M has a single PCIe Gen 2 host controller. Many Venice models have an on-board PCIe Gen 2 switch which allows the board to support more than 1 PCIe endpoint device.
A PCIe switch operates like a PCI bridge such that it will create additional subordinate busses.
Please see the user manual for the specific board model following the links here
There are several factors that can affect PCIe performance. The most obvious factor is how many lanes (pairs of TX/RX SERDES channels) you have: 1x, 2x, 3x, 4x etc which are pure multipliers to the rates that can be achieved over a single lane. The next most obvious factor is what generation of PCIe your host controller (root complex or RC) and device (endpoint or EP) supports: Gen1, Gen2, Gen3 etc which factors into the transfer rate and data transfer overhead . Digging deeper into the Transaction Layer Packet (TLP) overhead is not as obvious as RC's and EP's have varying max payload packet sizes. Digging even deeper than this you will get to specific limitations within the i.MX8M PCIe host controller.
The i.MX8M PCIe host controller has a limit where if the data transfer size exceeds 400 Bytes, the number of inbound MWr TLP transactions that the controller can support is up to the combination of 12 headers and 400 bytes of data payload as long as neither is exceeded. Higher performance can be obtained by having hte i.MX8M host controller issue outbound MRd transactions instead of using inbound MWr. See AN13164 iMX8MP PCIe Bandwidth Analysis.
Reset signals are routed to the Mini-PCIe sockets. On boards without a switch this is an i.MX8M GPIO and on boards with a PCIe switch an i.MX8M GPIO drives the PERST# of the switch and the switch automatically controls the PERST# signal going to each down-stream socket and they can not be independently controlled.