Gateworks System Controller (GSC)

The Gateworks System Controller (GSC) is a device present across various Gateworks product families that provides a set of system related feature such as the following (refer to the board hardware user manuals to see what features below are present):

• Real Time Clock (RTC)
• System voltage/temperature monitoring
• Software controllable Fan controller (6 temperature setpoints)
• General Purpose Input / Output (GPIO) expansion
• Software Configurable User Push-Button
• EEPROM storage
• Software Configurable Deep Sleep with RTC Wakeup
• Alternate Boot device selection and auto-selection
• Tamper detection
• GPS Active Antenna short-circuit auto-detect and recover
• Hardware Watchdog
• Reset Monitor
• Software field-upgradable firmware

The GSC communicates with the host CPU over the i2c bus and uses the following 7-bit i2c slave addresses:

• 0x20 - GSC configuration registers
• 0x21 - GSC software update registers
• 0x23 - PCA9555 emulated I/O (common industry standard GPIO port expander)
• 0x29 - system monitor (similar to industry standard AD7418 but with modified register set - see below)
• 0x50 - 24c04 emulated EEPROM (256B) (common industry standard EEPROM device)
• 0x51 - 24c04 emulated 256 byte EEPROM (common industry standard EEPROM device)
• 0x52 - 24c04 emulated 256 byte EEPROM (common industry standard EEPROM device) (some models only)
• 0x53 - 24c04 emulated 256 byte EEPROM (common industry standard EEPROM device) (some models only)
• 0x68 - DS1672 emulated RTC (common industry standard device)

GSC versions

The latest Gateworks products use a third generation GSC. The following generations exist:

Family	Board	GSC version
Newport	all	v3
Ventana	all	v2
Laguna	GW2388/GW2391/GW2387	v2
Laguna	GW2380/82/83	v1
Rincon	all	v1

The various generations of GSC versions are:

• v1: MSP430F2132
• v2: MSP430F2252
  • additional RAM/FLASH space (additional user eeprom regions)
  • additional ADC
  • added FAN controller
  • added Alternate boot device support
• v3: MSP430FR58471
  • additional RAM/FLASH space
  • additional ADC
  • improved I2C interface eliminates occasional I2C NAK's
  • reduced power consumption resulting in longer battery life (3.8Y -> 5Y)
  • resolves 'high power draw state' when inserting a battery while board powered off

Real Time Clock

The GSC contains a Real Time Clock (RTC) which emulates a Dallas Semiconductor DS1672, or equivalent. The RTC is battery backed to retain time information when SBC power is removed. The I2C address for the RTC is 0x68h. The RTC is compatible with the standard Linux ds1672 RTC driver and thus works with the standard Linux RTC device API documented ​here. The RTC device will be /dev/rtc0 and adheres to the standard ioctl and sysfs API's.

The most common Linux RTC commands are (refer to the linux man pages for more info on the commands and the available time/date formats):

• Write System Time and Date from Console:

  date #time and date you would like to write
  

• Write Real Time Clock Time and Date from System Time:

  hwclock -w
  

• Read Time and Date from System Time:

  date
  

• Read Time and Date from Real Time Clock:

  hwclock -r
  

• Example: Set the system time to a specific date, then set the RTC from that date, then read the RTC:

  > date -s 201303041744.42
  Mon Mar  4 17:44:42 UTC 2013
  > hwclock -w
  > hwclock -r
  Mon Mar  4 17:44:47 2013  0.000000 seconds
  

Note that typical Linux based systems use a Real Time Clock as such:

• on system boot, the hardware clock (RTC) sets the time of the system clock (the system clock ticks based on the CPU's timer). This is typically done in an init script using hwclock but sometimes can be done from an RTC kernel driver (which is the case for the GSC RTC supported by the ds1672 driver - upon driver init, the system time will be set from the GSC RTC)
• a Network Time Protocol (NTP) client runs in the background and periodically updates the system clock (not the hardware RTC) based on the time of an Internet Time Server
• on system shutdown (ie, a 'clean' or 'user prompted' shutdown) the system will set the RTC value from the system clock (because it is assumed that a system clock sync'd with an Internet Time Server is more accurate than an RTC). This is typically done in a shutdown init script.
• Note that none of the above may be typical of an Embedded Linux OS

System Temperature and Voltage Monitor

The GSC implements system voltage and temperature monitoring (similar to industry standard AD7418) at i2c slave address 0x29. For each analog to digital converter (ADC) input, the value can be read at a register offset. The register mapping differs depending on the version of the GSC:

GSC v3 (Newport)

The following 16-bit registers (MSB first, LSB second) are available:

system monitor registers:

Name	Register	Note
Board Temp	0x06	Deg C/10
VBatt	0x08	Volts/1000
FAN0	0x0A	Fan setpoint 0 1
FAN1	0x0C	Fan setpoint 1 1
FAN2	0x0E	Fan setpoint 2 1
FAN3	0x10	Fan setpoint 3 1
FAN4	0x12	Fan setpoint 4 1
FAN5	0x14	Fan setpoint 5 1
FAN_TACH	0x16	FAN TACH pulses per second
ADC A0	0x80	Raw ADC value 2
ADC A1	0x82	Raw ADC value 2
ADC A2	0x84	Raw ADC value 2
ADC A3	0x86	Raw ADC value 2
ADC A4	0x88	Raw ADC value 2
ADC A5	0x8A	Raw ADC value 2
ADC A6	0x8C	Raw ADC value 2
ADC A7	0x8E	Raw ADC value 2
ADC A8	0x90	Raw ADC value 2
ADC A9	0x92	Raw ADC value 2
ADC A10	0x94	Raw ADC value 2
ADC A11	0x96	Raw ADC value 2
ADC A12	0x98	Raw ADC value 2
ADC A13	0x9A	Raw ADC value 2
ADC A14	0x9C	Raw ADC value 2
ADC A15	0x9E	Raw ADC value 2
ADC A30	0xA0	Raw ADC value 2
ADC A31	0xA2	Raw ADC value 2

1. See fan below
2. Consult individual board hardware manual or the Linux device-tree for a description of what voltage rail this is and what voltage divider is applied in order to scale it. The Newport Linux kernel and BDK use information from the Linux Device-tree to scale and name these ADC's

A Linux 'Hardware Monitor' (hwmon) driver is available which provides simple standard access to the above temperature/voltage registers via sysfs. The arguments have been given labels which define the source. The user can “cat” the label to determine the source.

Note that the standard sysfs entries for hwmon drivers are such that temperatures are in millidegrees celcius and voltages are in millivolts.

GSC v1/v2 (Laguna/Ventana)

A single temperature sensor provides the board temperature in a 16-bit value (MSB first, LSB second) at register offset 0x00 in degrees Celcius. The voltage based ADC inputs provides a voltage (millivolt) as a 24-bit value (MSB first, LSB last). The ADC measurements are performed once per second (1Hz).

The following table shows the set of registers supported (Note each board supports a subset of these - an unsupported {source} will return a full-scale reading of 16,777,215)

system monitor registers:

Name	Register	Parameter	Units	Description
temp1	0x00	Temperature	Deg C/10	SBC Temperature
vin	0x02	Voltage	Volts/1000	SBC Input Voltage
3p3	0x05	Voltage	Volts/1000	3.3V
bat	0x08	Voltage	Volts/1000	GSC Coin Cell Battery
5p0	0x0B	Voltage	Volts/1000	5.0V
core	0x0E	Voltage	Volts/1000	Primary Processor Core
cpu1	0x11	Voltage	Volts/1000	Primary Processor 1 Operating
cpu2	0x14	Voltage	Volts/1000	Primary Processor 2 Operating
dram	0x17	Voltage	Volts/1000	System DRAM Memory
ext_bat	0x1A	Voltage	Volts/1000	GSC External Battery (not in use)
io1	0x1D	Voltage	Volts/1000	Miscellaneous
io2	0x20	Voltage	Volts/1000	Miscellaneous
pcie	0x23	Voltage	Volts/1000	PCI Express
io3	0x26	Voltage	Volts/1000	Miscellaneous
io4	0x29	Voltage	Volts/1000	Miscellaneous
fan0_point0	0x2C	Temperature	Deg C/10	Fan controller set point 0
fan0_point1	0x2E	Temperature	Deg C/10	Fan controller set point 1
fan0_point2	0x30	Temperature	Deg C/10	Fan controller set point 2
fan0_point3	0x32	Temperature	Deg C/10	Fan controller set point 3
fan0_point4	0x34	Temperature	Deg C/10	Fan controller set point 4
fan0_point5	0x36	Temperature	Deg C/10	Fan controller set point 5

• Note that the above descriptions are board-specific. Please see the board ​Hardware User Manual 'System Temperature and Voltage Monitor' section for details.

A Linux 'Hardware Monitor' (hwmon) driver is available in OpenWrt which provides simple standard access to the above temperature/voltage registers via sysfs. The arguments have been given labels which define the source. The user can “cat” the label to determine the source. See the following examples listed below.

• Read board Input Voltage:

  DIR=$(find /sys/bus/i2c/devices/0-0029/ -name in0_input)
  DIR=${DIR%/*}
  cat $DIR/in0_label
  cat $DIR/in0_input
  

• Output a list of all sources and their values:

  # DIR=$(find /sys/bus/i2c/devices/0-0029/ -name in0_input)
  # DIR=${DIR%/*}
  # cd $DIR
  # for F in *;do echo -n “$F: “;cat $F;done
   fan0_point0: 300
   fan0_point1: 330
   fan0_point2: 360
   fan0_point3: 390
   fan0_point4: 420
   fan0_point5: 450
   in0_input: 23569
   in0_label: vin
   in10_input: 16777215
   in10_label: io2
   in11_input: 1505
   in11_label: pci2
   in12_input: 16777215
   in12_label: current
   in1_input: 3395
   in1_label: 3p3
   in2_input: 3403
   in2_label: bat //coincell battery
   in3_input: 4836
   in3_label: 5p0
   in4_input: 1237
   in4_label: core
   in5_input: 16777215
   in5_label: cpu1
   in6_input: 16777215
   in6_label: cpu2
   in7_input: 1802
   in7_label: dram
   in8_input: 16777215
   in8_label: ext_bat //not currently in use
   in9_input: 2466
   in9_label: io1
   temp0_input: 442
   temp0_label: temp
  

  • Note 16777215 indicates a default value and item is not connected.

For systems without the GSC Hardware Monitor driver, values can be read directly through I2C: Example: Temperature is shown as register 0x00 and 0x01.

i2cget -f -y 0 0x29 1
0x01
i2cget -f -y 0 0x29 0
0xc0

Combining 0x01 and 0xc0, is 0x01c0, which comes out to be 448, which divided by 10, equals 44.8 Deg. C.

For Ventana i.MX6 processor temperature, see here

Battery Voltage Reading

The battery voltage rail (bat) cannot be measured until board power is turned off for two seconds or more. When power is off, the GSC monitors the battery voltage every 18 hours. When the board is fully powered on and booted into Linux, the battery voltage reading will be the last read voltage when the board was powered off. For always on applications where battery voltage needs to be accurate, it is suggested to have the GSC do a powercycle for two seconds at a convenient time to get an updated battery voltage reading.

Fan Controller

*Note: This feature is only on certain baseboards. Please consult the hardware manual.

A pulse width modulated (PWM) fan controller is supported by some boards. The GSC controller allows the fan speed to be varied based upon temperature to help reduce bearing wear and extend fan lifetime. The fan controller contains six temperature set points which correspond to duty cycles ranging from 50 to 100 percent (fully on). See the below chart for the PWM duty cycle versus temperature set points.

*Note: typically the PWM occurs on the ground pin, and the 5V is constant. However, consult the hardware manual to determine if your board uses that configuration.

Source	Default (°C/10)	Description
Fan0_point0	300	Set point 0 = 50% PWM duty cycle
Fan0_point1	330	Set point 1 = 60% PWM duty cycle
Fan0_point2	360	Set point 2 = 70% PWM duty cycle
Fan0_point3	390	Set point 3 = 80% PWM duty cycle
Fan0_point4	420	Set point 4 = 90% PWM duty cycle
fan0_point5	450	Set point 5 = 100% PWM duty cycle

• Note - The set point value represents temperature in °C/10 (only positive values allowed).

The fan controller temperature set points can be found in the /sys/class/hwmon directory along with the temperature and voltage monitor information (see previous section). The following examples show reading and writing to the fan set point register.

The fan controller setpoints are supported via the standard linux Hardware Monitor (hwmon) driver in the OpenWrt BSP. Some examples of configuration are:

• Read temperature set-point 0:

  DIR=$(find /sys/bus/i2c/devices/0-0029/ -name in0_input)
  DIR=${DIR%/*}
  # cat $DIR/fan0_point0 # read set point - default 30C
  300
  

• Set temperature set-point 0:

  DIR=$(find /sys/bus/i2c/devices/0-0029/ -name in0_input)
  DIR=${DIR%/*}
  echo 350 > $DIR/fan0_point0 # set to 35C
  

Always-on FAN for a constant voltage source

Occasionally users want to keep the FAN controller always-on in order to provide a constant voltage source.

To achieve a constant 5 volts for general use, it is possible to set the 100% PWM duty cycle fan point (fan0_point5) to 0. Because the fan controller does not accept negative temperatures, this means it will always be on while the temperature is greater than 0C (or negative as the fan controller does not accept negative temperatures).

Examples:

• FAN output always on 100% duty cycle (constant 5V):

  DIR=$(find /sys/bus/i2c/devices/0-0029/ -name in0_input)
  DIR=${DIR%/*}
  echo 0 > $DIR/fan0_point5; set to 0C
  

General Purpose Input and Output (GPIO)

The GSC contains a General Purpose Input and Output (GPIO) port expander which emulates a Texas Instruments PCA9555, or equivalent. The Gateworks board support package maps the PCA9555 GPIO base number to 100 by default (Though this may vary). The functionality supports setting each GPIO signal as an input or output with read-back. For more information on the PCA9555 see the ​PCA9555 Datasheet. The I2C address for the PCA9555 is 0x23h.

Each board level product has a unique GPIO configuration. Refer to the specific board hardware user manual for more details.

The most common Linux GPIO commands are:

• Determine GPIO configuration and settings:

  cat /sys/kernel/debug/gpio
  

• Configure GPIO 'n' as Input:

  echo in > /sys/class/gpio/gpio<n>/direction
  

• Configure GPIO 'n' as Output:

  echo out > /sys/class/gpio/gpio<n>/direction
  

• Read Input GPIO 'n':

  cat /sys/class/gpio/gpio<n>/value
  

• Write Output GPIO 'n' to Logical 1:

  echo 1 > /sys/class/gpio/gpio<n>/value
  

• Write Output GPIO 'n' to Logical 0:

  echo 0 > /sys/class/gpio/gpio<n>/value
  

Note that some boards route several GSC based GPIO's to various off-board connectors for use as general purpose digital I/O (DIO) or tamper switch circuits. As such, these ports are configured as inputs by default and if unconnected (un-terminated electrically) can cause spurious IRQ_GPIO_CHANGE interrupt events when enabled. This is typically the case with an unused tamper circuit.

To avoid spurious interrupts if you have un-terminated GPIO's configure them as outputs. Note that the GSC will not allow a dedicated input GPIO to be set as an output so there is no harm in just setting all to outputs as long as you don't have one of them connected to a circuit off-board that will cause undesired effects if driven high or low.

For example to set all P0 and P1 bits as outputs from Linux:

i2cset -f -y 0 0x23 6 0x00 # configure GPIO P0_DIR as outputs
i2cset -f -y 0 0x23 7 0x00 # configure GPIO P1_DIR as outputs

See also:

• OpenWrt GPIO
• GPIO

User Pushbutton

The GSC offers software controllable user pushbutton configuration. The GSC can be configured to perform a hardware function or raise a host CPU interrupt on certain configurations:

• hardware reset (1x quick press-and-release) - default configuration
• software interrupt on state change (r30 firmware and above)
• software interrupt on long (>700ms) press-and-hold
• erase security key EEPROM on 3x quick press-and-release
• reset board and boot from alternate boot device on 5x quick press-and-release (for boards that have an alternate boot device)

The default configuration of the GSC is to perform a hard reset on a quick press-and-release. To change this you need to set the CTRL_0 register. For example:

• enable all button events

  i2cset -f -y 0 0x20 0 0x00 # disable pushbutton hard reset
  i2cset -f -y 0 0x20 11 0xff # enable all interrupts
  

  • please see here regarding un-terminated inputs causing spurious GPIO_CHANGE events

The gsc-input kernel driver will produce Linux Input events for the above interrupts.

In addition, the user pushbutton state is available on a GPIO in case you need to do anything more flexible than the above built-in interrupt functionality:

Family	Boards	gsc gpio	linux gpio
Ventana	GW5xxx	i2c/0-0023 pca9555 gpio0	gpio240
Laguna	GW2380/GW2382/GW2383	i2c/0-0023 pca9555 gpio8	gpio108
Laguna	GW2387/GW2388/GW2391	i2c/0-0023 pca9555 gpio0	gpio100

An example of when you would want to use the pushbutton gpio is if you want to do something like determine if the user pushbutton has been held for a certain amount of time. This type of event is not available via the GSC interrupts and thus the gsc-input kernel driver because it involves starting a timer on a button-down event and counting the time expired before any button-up event occurs.

The Linux kernel gpio-keys and gpio-keys-polled (and OpenWrt gpio-button-hotplug) drivers can be used to create Linux Input events from pushbuttons connected to GPIO's however if you want this functionality, you can use the gsc-input driver which is already enabled in the Gateworks BSP's. Note that the gpio-keys/gpio-keys-polled/gpio-button-hotplug drivers use the pushbutton gpio in a kernel driver therefore you can not export the gpio to userspace, where-as the gsc-input driver uses GSC interrupts for its information and therefore does not take control over the gpio.

BSP Specific Notes:

• OpenWrt:
  • the gsc-input kernel driver can be used to catch the built-in interrupts which can be produced by various pushbutton events
  • the gpio-button-hotplug driver is enabled uses the pushbutton GPIO therefore it must be disabled if you want to export it for userspace access. Most likely you can get the functionality you need by using the OpenWrt button-hotplug-gw package.
    • The gpio-button-hotplug out-of-tree driver is an OpenWrt custom driver that takes the place of the in-kernel gpio-keys (KEYBOARD_GPIO) and gpio_keys_polled (KEYBOARD_GPIO_POLLED) drivers and instead of emiting linux input events it emits uevent messages to the button subsystem which tie into the OpenWrt hotplug daemon.
    • Note that for Ventana this uses the gpio_keys device-tree node to map gpio-240 to the 'user_pb' button event.
    • to disable this driver to be able to export the pushbutton gpio either by removing the device-tree node (Ventana only) or by disabling KEYBOARD_GPIO/KEYBOARD_GPIO_POLLED drivers in the OpenWrt kernel config.
    • The only real benefit of using your own program to monitor the pushbutton gpio over the OpenWrt hotplug method is that you can catch 'held' events without waiting for a button release because the gpio-button-hotplug OpenWrt driver only catchings button down and up events (it does not fire off a timer on a button down event and periodically emit hotplug events as the button is still held down)
  • see OpenWrt GPIO for more info on how to use GPIO's as buttons in OpenWrt
  • see also ​http://wiki.openwrt.org/doc/howto/hardware.button
• Yocto:
  • the gsc-input kernel driver can be used to catch the built-in interrupts which can be produced by various pushbutton events
• Android:
  • the gsc-input kernel driver can be used to catch the built-in interrupts which can be produced by various pushbutton events. There is also a key-layout file that maps these events to Android keys.

In Summary you have a few options for performing actions based on user pushbutton events depending on your needs and BSP.

See also:

gsc-interrupts

Code Examples for software user pushbutton detection

The following example will configure the GSC for SW pushbutton interrupt and read the PB state by polling the GPIO (see above):

# clear R0.1 bit to disable pushbutton hard reset - taking care to not disturb other bits
R0=$(i2cget -f -y 0 0x20 0) && \
  R0=$((R0 & ~0x01)) && \
  i2cset -f -y 0 0x20 0 $R0 || echo i2c error
# export gpio240 to userspace (Note this value is board specific - see above table)
echo 240 > /sys/class/gpio/export
while [ 1 ]; do
  cat /sys/class/gpio/gpio240/value ;# PB state 0 or 1
done

A more appropriate method of detection may be to use the fact that the GSC has interrupt support and use the libc poll(2) function to block on the GPIO until it changes state. See Catching a GPIO from Userspace w/o polling for an example of how to do that.

See also:

• Catching a GPIO from Userspace w/o polling
• ventana/DigitalIO

EEPROM storage

The GSC emulates Atmel 24C04 EEPROM storage devices, or equivalent. The EEPROM functionality supports 4Kbits (512bytes) partitioned as shown below. The EEPROM is supported in Linux. The 7-bit I2C base address is 0x50.

Address	Device Address	Size (bytes)	Function
0x000-0x0FF	0x50: 0x00-0xFF	256	User EEPROM space
0x100-0x17f	0x51: 0x00-0x7F	128	Board Info EEPROM 1
0x180-0x1DF	0x51: 0x80-0xDF	96 5	Secure Key EEPROM 2
0x1E0-0x1FF	0x51: 0xE0-0xFF	32	Reserved
0x200-0x2FF	0x52: 0x00-0xFF	256	User EEPROM space 3
0x300-0x3FF	0x53: 0x00-0xFF	256	User EEPROM space 3

1. Board Info EEPROM is reserved for Gateworks
   • can be write protected by enabling EEPROM_WP_BOARDINFO (R15.1)
   • Information about board serialnum, model, manufacturing date, etc can be found in the EEPROM - see here for details
2. Secure Key EEPROM is erased if:
   • pushbutton is activated 3 times in quick succession (press-and-released <700ms delay between each activation). This function is enabled with R0.1
   • Tamper circuit has been activated (for boards supporting a tamper switch/header)
   • The GSC battery is depleted or is removed for more than 10 seconds
   • Note that these cases will always erase the Secure Key EEPROM region regardless of the Write Protect bits
3. additional 4Kbits (512bytes) available on GW2387/GW2388/GW2391)
4. There are 2 bits in R1 (GSC_CTRL_1) which act as a Write Protect for EEPROM regions:
   • EEPROM_WP_ALL (R15.0) will dissalow user i2c writes to all EEPROM regions (does not affect secure key erasure cases)
   • EEPROM_WP_BOARDINFO (R15.1) will dissallow user i2c writes to the Board Info EEPROM region
5. The GSC v3 used on the Newport product family provides 128 bytes of Secure Key area instead of 96.

EEPROM Secure Key Example

The secure key area starts at 0x51 offset 0x80 and extends for 96 bytes for GSC v1/v2 (Laguna/Ventana) and for 128 bytes for GSC v2 (Newport).

To see the secure key, you can use the command i2cdump from the command line: (starts with the ASCII values of D3 and ends with w in below example)

> i2cdump -f -y 0 0x51
No size specified (using byte-data access)

<<--------------- HEX GRID --------------------->>     << ASCII VALUE>>
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 d0 12 a9 ef f8 00 d0 12 a9 ef f9 ff ff ff ff    .?????.?????....
10: ff ff ff ff ff ff ff ff cb 5b 09 00 ff ff ff ff    ........?[?.....
20: 11 27 20 13 ff ff ff ff ff ff ff 05 0c 02 18 08    ?' ?.......?????
30: 47 57 35 32 30 30 2d 53 50 32 38 33 2d 41 00 00    GW5200-SP283-A..
40: 06 00 b5 4d 33 f0 01 00 c9 00 00 00 00 00 25 d0    ?.?M3??.?.....%?
50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
80: 44 33 ff ff ff ff ff ff ff ff ff ff ff ff ff ff    D3..............
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 77    ...............w
e0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX
f0: XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX    XXXXXXXXXXXXXXXX

To set the bytes from the command line, use a i2cset command. This example shows us writing a 0x3344 of size w (word, 2 bytes) at the beginning of the Secure Key storage at 0x80. The 0x51 is the i2c device address which will remain the same as according to the above information.

i2cset -f -y 0 0x51 0x80 0x3344 w

To Write a single byte:

i2cset -f -y 0 0x51 0x80 0x33

Custom Serial Number Example

For customers who need to add their own serial number, they can write it in the userspace EEPROM space at address 0x50 as shown in the table above.

Here, a customer specific serial number is created in the userspace EEPROM. For example using the first 6 bytes of userspace EEPROM to store a 6digit serial number in ascii representation:

i2cset -f -y 0 0x50 0x0 0x3535 w
i2cset -f -y 0 0x50 0x2 0x3737 w
i2cset -f -y 0 0x50 0x4 0x3939 w

Then, a i2cdump will show the serial number stored:

> i2cdump -f -y 0 0x50
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 35 35 37 37 39 39 ff ff ff ff ff ff ff ff ff ff    557799..........
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff    ................

To retrieve it, use the i2cget command:

> i2cget -f -y 0 0x50 0x0 w
0x3535

Hardware Sleep and Wake

The GSC has the ability (on the Laguna, Ventana, and Newport product family) has the ability to put the board into a 'Hardware Sleep' mode by disabling the primary power supply. This is very useful in many applications that do not require 24 hour operation and need to save power. In this mode the only item drawing power is the GSC itself (powered by a coin-cell battery). The GSC will 'wake' the board again by enabling the primary power supply when the RTC reaches the time defined in the GSC_SLEEP_WAKE register. The wakeup time can be set to an absolute RTC time by writing to GSC_SLEEP_WAKE or be set relative to the current RTC value by setting the GSC_SLEEP_ADD register and latching it via setting R1.2.

A pushbutton press will also wake the board unless the SLEEP_NOWAKEPB (R1.3) is enabled.

• NOTE : If performing sleep without a coin cell battery, a maximum of 4 seconds should be used for resetting the board. Anything longer may put the board to 'sleep' and not allow it to wake up without pressing the pushbutton or unplugging and plugging in the main power supply.

Board sleeping Example

The preferred method is to use the sysfs powerdown hook from the GSC driver as this takes care of the math and retries for you:

• Using the gsc-driver:

  echo 300 > /sys/bus/i2c/devices/0-0020/powerdown # sleep for 5 mins
  

• Manually writing to GSC (if you don't have the GSC driver)

The following example will sleep the board for 10 seconds by setting the “add timer” to 10 seconds (from the current time) and then putting the board to sleep. This example uses the Linux I2C utilities.

SECS=300 ;# 5 mins
i2cset -f -y 0 0x20 6 $((SECS % 256)); SECS=$((SECS >> 8))
i2cset -f -y 0 0x20 7 $((SECS % 256)); SECS=$((SECS >> 8))
i2cset -f -y 0 0x20 8 $((SECS % 256)); SECS=$((SECS >> 8))
i2cset -f -y 0 0x20 9 $((SECS % 256))
# set add time bit - taking care to not disturb other bits
R1=$(i2cget -f -y 0 0x20 1) && \
  R1=$((R1 | 0x04)) && \
  i2cset -f -y 0 0x20 1 $R1 || echo i2c error
# set sleep enable and sleep activate bits - taking care not to disturb other bits
R1=$(i2cget -f -y 0 0x20 1) && \
  R1=$((R1 | 0x03)) && \
  i2cset -f -y 0 0x20 1 $R1 || echo i2c error

The board will go to sleep and then wake up after 5 minutes (300secs). If you wanted the board to wakeup at a specific date/time regardless of the current RTC date/time you could set R2-5 to the number of seconds since the epoch (date +%s will show current system time in seconds) instead of using the R6-R9 'relative time' registers.

GSC Reboot

The GSC can also be used to reboot the board. See the following link for more info:

• Safe GSCReboot Script

Alternate Boot Device

Some Gateworks Laguna family products (GW2388) have an Alternate boot device that can be used for alternate firmware images, such as a flash recovery image. There are 2 ways that you can instruct the GSC to boot to the alternate boot device vs the primary boot device:

1. Press-and-release the user pushbutton 5 times in quick succession (see R0.3 (PB_BOOT_ALTERNATE) below)
2. Use the 'Auto Switch Boot' feature

More details on using the Alternate Boot Device can be found here.

Auto Switch Boot Device

If the board is equipped with an Alternate Boot Device you can enable the GSC's Auto Switch Boot feature by setting R1.6 (SWITCH_BOOT_ENABLE). When a board powers on with this bit set, the watchdog timer will be set for a 30 second timeout when the board is powered on. If this timer expires the GSC will toggle the boot device and power-cycle the board. You can disable the timer for the current boot by setting R1.7 (SWITCH_BOOT_CLEAR) (it will be re-armed on the next power cycle in SWITCH_BOOT_ENABLE has not been cleared).

For example, if you a supporting firmware updates in your product but want a mechanism to ensure a power loss or other event during a firmware update does not render your device recoverable you can enable this feature and put a 'recovery image' on the alternate boot device. In this example both firmware images (the primary and the alternate) should set R1.7 within 30 seconds of bootup if that firmware image is desirable. If either image fails to set R1.7 within the 30 seconds, the board will automatically boot to the other device.

More details on using the Auto Switch Boot Device can be found here.

Tamper Detection

Some boards have a Tamper Detect circuit implemented either as a physical pushbutton on the board and/or a header that can have an external switch wired to it. The circuit implemented is a normally open switch to board ground (GND).

For these boards you can enable the GSC's Tamper Detect feature by setting bit R0.5 (TAMPER_DETECT) and the accompanying interrupt register bit R11.5 (IRQ_TAMPER_DETECT). Once these bits are set any tamper event produced by a switch closing and the signal conducting to board ground will do the following:

1. set IRQ_TAMPER_DETECT interrupt source bit
2. erase the secure key EEPROM section
3. produce a GSC interrupt (if board is powered)

• Note: Older revision Ventana models may require a modification for this feature (Errata HW4), please contact factory at support@…

See also:

gsc-interrupts

GPS Active Antenna short-circuit auto-detect and recover

On some Gateworks products, the Active GPS Antenna has a short-circuit detection circuit that will disable the antenna power if an excessive current draw is detected (ie a short). On some of these products, the GSC will re-enable the antenna power every second in case the short has been removed or replaced. The reason for this protection is two-fold:

1. over-current protection keeps board power available if an antenna short/fault has occurred
2. a shorted/faulty antenna can be replaced without having to power down the board

Products with GPS antenna protection (GPS is not loaded on all model variants, contact sales@… for details):

Family	Board	Overcurrent Protection	Recovery
Newport	GW630X	Current Limit	No
	GW640X	Current Limit	No
Ventana	GW51XX	Current Limit	No
	GW52XX	Current Limit	No
	GW53XX	Yes	Yes
	GW54XX	Yes	Yes
	GW553X	Yes	No
Laguna	GW2387	Yes	Yes
	GW2388	Yes	No
	GW2391	Yes	Yes

GSC Interrupts

The Gateworks System Controller has an interrupt signal to the host processor which it asserts when an event has occurred worth notifying the host about. The GSC_INTERRUPT_ENABLE register defines what events can trigger an interrupt and an interrupt service routine can query the GSC_INTERRUPT_STATUS register to see what events are present. The interrupt remains asserted until all status bits are cleared by writing 0's to those bits in the GSC_INTERRUPT_STATUS register.

See also:

• GSC_INTERRUPT_STATUS register
• GSC_INTERRUPT_ENABLE register

IRQ_PB interrupt

The IRQ_PB interrupt occurs if the user pushbutton has been pressed then released within 700ms thus signifying a quick 'press-and-release' event. Note that the PB_HARD_RESET bit must be cleared in the GSC_CTRL_0 register for this to occur otherwise a pushbutton will cause a hard board reset.

See also:

• pushbutton

IRQ_SWITCH_HOLD interrupt

The IRQ_SWITCH_HOLD interrupt occurs if SWITCH_HOLD is enabled in the GSC_CTRL_0 register and the user pushbutton was held for over 1 second.

See also:

• pushbutton

IRQ_SECURE_KEY_ERASED interrupt

The IRQ_SECURE_KEY_ERASED interrupt occurs after the user key EEPROM area has been erased. This can occur because of either a tamper event (see TAMPER_DETECT) or because 3x quick button press-and-release events have occurred (see PB_CLEAR_SECURE_KEY).

See also:

• pushbutton
• EEPROM

IRQ_EEPROM_WP interrupt

The IRQ_EEPROM_WP interrupt occurs if the GSC_EEPROM_WP_ALL or GSC_EEPROM_BOARDINFO bits are set in the GSC_WRITE_PROTECT register and a write protect violation has occurred.

See also:

• EEPROM

IRQ_GPIO_CHANGE interrupt

The IRQ_GPIO_CHANGE interrupt occurs if a GSC GPIO which is configured as an input has changed state. Note that the GSC GPIO controller emulates a PCA9555 chip.

Note that this interrupt needs to be enabled if you wish to sense user pushbutton press and release events independently (for example, you are trying to implement your own timing, or using the Linux gpio-keys driver which creates Linux input events from GPIO based buttons).

Note that some boards route one or more GSC based GPIO's to various off-board connectors for use as general purpose digital I/O (DIO) or tamper switch circuits. As such, these ports are configured as inputs by default and if unconnected (un-terminated electrically) can cause spurious IRQ_GPIO_CHANGE interrupt events when enabled.

To avoid this make sure you configure unused inputs as outputs. Note that the GSC will not allow a dedicated input GPIO to be set as an output so there is no harm in just defaulting all to outputs as long as there are no GPIO's connected to off-board circuits that will cause undesirable affects if drive high or low.

For example to set all P0 and P1 bits as outputs from Linux:

i2cset -f -y 0 0x23 6 0x00 # configure GPIO P0_DIR as outputs
i2cset -f -y 0 0x23 7 0x00 # configure GPIO P1_DIR as outputs

See also:

• GPIO

IRQ_TAMPER_DETECT interrupt

The IRQ_TAMPER_DETECT interrupt occurs if TAMPER_DETECT has been enabled in the GSC_CTRL_0 register and the tamper circuit is broken. Only certain products have one or more tamper circuits. If supported the tamper signals are connected to a normally closed to ground button.

See also:

• Tamper Detection

IRQ_WDOG_TIMEOUT interrupt

The IRQ_WDOG_TIMEOUT interrupt indicates that the GSC watchdog caused a board level power cycle and as such can't be caught via software (as the board was power cycled) but can be detected at power-on as the reason for reset.

Note that the Ventana bootloader reads and clears this status register but displays the result.

See also:

• Hardware Watchdog

Hardware Watchdog

Ventana and Laguna boards with GSC v2 can benefit from a GSC Watchdog (requires v44 or later of GSC firmware). Note that Newport boards with a GSC v3 do not benefit from a GSC Watchdog as the external reset on the CN80XX/CN81XX is asserted when the CPU watchdog expires and is monitored by the GSC. The GSC on these boards will cause a primary board power supply reset when this occurs.

A watchdog is a common feature which allows a timer to be configured such that a reset occurs if that timer expires. A software component will typically enable the watchdog timer and restart it periodically before the timer expires based on some conditions. Usually there is no specific condition so the timer gets restarted (avoiding a system reset) unless the CPU running that software hangs.

Systems that want to place more criteria on the condition of restarting the watchdog can do so, such as checking various statistics or states. For example, you may wish to reset the board if the network connection ever goes away.

Most modern CPU's have built-in watchdog elements, which will reset the CPU and sometimes drive an external signal which can reset various components on the board. For example, our Laguna products with NOR flash will reset the NOR flash when a watchdog reset occurs because we have found that without doing so the processor can hang on a CPU reset. The linux kernel supports CPU watchdogs with a driver and a well known userspace API, but in this scenario the watchdog is not enabled (and thus not protecting against hangs etc) until userspace init is reached.

Sometimes, however, a CPU watchdog isn't adequate because there may be an issue which you are trying to protect against such as a hang before the watchdog is even enabled or perhaps an issue where a peripheral isn't reset on a watchdog event (because the hardware doesn't have a reset pin for example, or the board design did not connect it).

Because the Gateworks System Controller has the ability to disable a board's primary power supply its the perfect place to implement a hardware watchdog. When the GSC's watchdog trips, it will power cycle the board vs a 'reset'. Furthermore, because the GSC watchdog re-arms on power-up when enabled you can protect against hangs over the full power-up of the board: primary program loader (ie CPU boot ROM), secondary program loader (oe uboot), kernel (ie Linux kernel), and userspace.

Example usage:

• Enable watchdog (with latest Ventana u-boot):

  gsc wd enable 30 # enable watchdog for 30s timeout
  gsc wd enable 60 # enable watchdog for 60s timeout
  

• Enable watchdog (from older Ventana u-boot)

  i2c dev 0 # GSC is on the first of several i2c busses
  i2c mw 0x20 1 0x20 1 # set R1=0x20 to enable watchdog for 30s timeout
  

• Enable watchdog (from Laguna u-boot)

  imw 0x20 1 0x20 1 # set R1=0x20 to enable watchdog for 30s timeout
  imw 0x20 1 0x30 1 # set R1=0x30 to enable watchdog for 60s timeout
  

• Enable watchdog (from Linux)

  i2cset -f -y 0 0x20 1 0x20 # set R1=0x20 to enable watchdog for 30s timeout
  i2cset -f -y 0 0x20 1 0x30 # set R1=0x30 to enable watchdog for 60s timeout
  

• Disable watchdog (from latest Ventana u-boot)

  gsc wd disable
  

• Disable watchdog (from older Ventana u-boot)

  i2c dev 0 # GSC is on the first of several i2c busses
  i2c mw 0x20 1 0 1 # disable watchdog
  

• disable watchdog (from Laguna u-boot-2008)

  imw 0x20 1 0 1 # disable watchdog
  

• disable watchdog (from Linux)

  i2cset -f -y 0 0x20 1 0x00 # clear R1 to disable watchdog
  

In the above examples, notice that you are overwriting other bits that you may care about in R1 such as sleep enable. If you want a more foolproof way of adjusting just the bit you care about mask out the bits you want to set then OR in the value you want to set them to. For example, if you wish to set R1.4=0 and R1.5=1 you could to the following in shell:

R1=$(i2cget -f -y 0 0x20 1) && \
  R1=$((R1 & ~0x30)) && \
  R1=$((R1 |  0x20)) && \
  i2cset -f -y 0 0x20 1 $R1 || echo i2c error

Notes:

• Once enabled, the GSC watchdog will re-arm on a power-up event (so that the board is protected from power-up onward). Because of this feature, if you have enabled the GSC watchdog:
  • if you break out of the bootloader you will need to disable the watchdog manually (see above)
  • if you use jtag_usb to program firmware you will need to be sure to use the most recent version which knows to disable the GSC watchdog
• The Ventana GSC always uses the watchdog on power-up to cover some IMX6 errata which can cause the board to fail to boot from NAND. The bootloader disables the watchdog unless you have enabled it manually.
• If you encounter difficulties once you have enabled the watchdog (ie your software is not resetting or disabling the watchdog, or your can't program the board via uboot or jtag) you can simply remove the GSC battery for 10seconds to reset the GSC to the default state where the watchdog is not enabled (this will of course reset all other registers you may have changed including the RTC).
• see below for details on using the GSC watchdog via the Linux kernel driver and making sure you have a userspace application that tickles it
• see watchdog for more info on watchdogs in general

GSC Registers

The System Specialized Functions described above are configured via a set of GSC registers in an i2c slave device at the 7-bit address of 0x20.

GSC Registers:

Reg Number	Reg Name	Description
0	GSC_CTRL_0	Pushbutton Switch, CRC, Tamper Switch
1	GSC_CTRL_1	Sleep / Wakeup Control, Alternate Boot Device
2-5	GSC_SLEEP_WAKE_TIME	Sleep Wakeup Timer
6-9	GSC_SLEEP_ADD	Sleep Wakeup Additive Timer
10	GSC_INTERRUPT_SOURCE	Interrupt Source
11	GSC_INTERRUPT_ENABLE	Interrupt Enable
12-13	GSC_FIRMWARE_CRC	Firmware CRC Value
14	GSC_FIRMWARE_VER	Firmware Version
15	GSC_WRITE_PROTECT	Write Protection

GSC_CTRL_0 (Register R0): Pushbutton Switch, CRC, and Tamper Switch configuration

Bit	Name	Description
0	PB_HARD_RESET	0 = Pushbutton Software Interrupt Generates GSC Interrupt (see R10.0/R11.0) 1 = Push button generates hard system reset to board when the button is activated and de-activated within 700ms
1	PB_CLEAR_SECURE_KEY	0 = Clear Secure Key EEPROM disabled 1 = Clear GSC EEPROM user space when switch is activated three times with less than 700ms delay between each activation Generates GSC Intterupt
2	PB_SOFT_POWER_DOWN	0 = Soft Power Down disabled 1 = Soft Power Down enabled Hold down >1s to power down When powered down a momentary press will power up Generates push button interrupt
3	PB_BOOT_ALTERNATE	0 = Boot Alternate Device disabled. 1 = Boot Alternate Device Enabled The board will reset and boot from the Alternate Boot Device when the pushbutton is activated (quick press-and-release) 5 times in quick succession)
4	PERFORM_CRC	1 = Run CRC on GSC and store results in GSC_FIRMWARE_CRC (R12,R13) resets to 0 on completion of CRC
5	TAMPER_DETECT	0 = Do not activate tamper switch operation 1 = Activate tamper switch operation. When Activated, if the tamper switch is released, the contents in the EEPROM user space will be erased Generates tamper switch interrupt.
6	SWITCH_HOLD	0 = Switch hold disabled. 1 = Switch Hold On. When the switch is held down for >700ms an interrupt will be generated. See interrupt Enable / Status registers. (supported in rev29+)
7		Reserved

GSC_CTRL_1 (Register R1): Sleep Wakeup Timer Control

Bit	Name	Description
0	SLEEP_ENABLE	0 = Disable hardware sleep operation 1 = Enable hardware sleep operation
1	ACTIVATE_SLEEP	0 = Do not activate hardware sleep operation 1 = Activate hardware sleep operation (see GSC_SLEEP_WAKE)
2	LATCH_SLEEP_ADD	0 = Reserved 1 = Latch and add GSC_SLEEP_ADD registers to GSC_SLEEP_WAKE Resets to Zero on Completion
3	SLEEP_NOWAKEPB	0 = Wake from sleep on pushbutton 1 = do not wake on sleep until sleep wakeup time
4	WATCHDOG_TIME	0 = 30 second timeout 1 = 60 second timeout
5	WATCHDOG_ENABLE	0 = disable watchdog 1 = Enable / Reset watchdog timer
6	SWITCH_BOOT_ENABLE	0 = Auto Switch boot disabled 1 = Auto Switch boot enabled Note this is set and used at powerup by the GSC as a boot watchdog on Ventana boards
7	SWITCH_BOOT_CLEAR	Auto Switch boot clear Set to disable auto switch boot countdown timer Note this is set and used at bootup by the bootloader as a boot watchdog on Ventana boards

GSC_SLEEP_WAKE_TIME (Registers R2-R5): Sleep Wakeup Time

Bit	Description
0-31	RTC Value to wake the board when in sleep (least significant byte first)

GSC_SLEEP_ADD (Registers R6-R9): Sleep Wakeup Time Additive

Bit	Description
0-31	Add to current RTC and store in GSC_SLEEP_WAKE_TIME latched with R1.2 (least significant byte first)

GSC_INTERRUPT_STATUS (Register R10): Interrupt Source

The GSC includes a single active-low level-triggered interrupt connected to an interrupt input on the ARM host processor. The GSC includes several possible interrupt sources with a control register to enable the desired interrupts and a status register to determine which are active. The following bits will indicate the cause of the host interrupt assertion which will remain asserted until all enabled bits are clear.

Bit	Name	Description
0	IRQ_PB	When set a pushbutton switch interrupt has occurred
1	IRQ_KEY_ERASED	When set a Secure Key erase operation has completed
2	IRQ_EEPROM_WP	When set an EEPROM WP violation occurred (write to EEPROM while GSC_EEPROM_WP_ALL or GSC_EEPROM_WP_BOARDINFO was enabled)
3		Reserved
4	IRQ_GPIO_CHANGE	When set a GPIO interrupt has occurred
5	IRQ_TAMPER_DETECT	When set a tamper switch interrupt has occurred
6	IRQ_WDOG_TIMEOUT	When set a watchdog timeout has occurred resulting in the board being reset
7	IRQ_SWITCH_HOLD	When set a 'switch hold' interrupt has occurred

For more information see gsc-interrupts

GSC_INTERRUPT_ENABLE (Register R11): Interrupt Enable (refer to bits above)

Bit	Name	Description
0	IRQ_PB	Set to enable pushbutton switch interrupt
1	IRQ_SECURE_KEY_ERASED	Set to enable Secure Key erase operation interrupt
2	IRQ_EEPROM_WP	Set to enable EEPROM WP violation interrupt
3		Reserved
4	IRQ_GPIO_CHANGE	Set to enable GPIO interrupt
5	IRQ_TAMPER_DETECT	Set to enable Tamer detect interrupt
6	IRQ_WDOG_TIMEOUT	Set to enable Watchdog timeout interrupt
7	IRQ_SWITCH_HOLD	Set to enable pushbutton switch 'hold' interrupt

For more information see gsc-interrupts

GSC_FIRMWARE_CRC (Register R12,R13): GSC Firmware CRC Value

Bit	Description
0-15	Contains the 16-bit cyclic redundancy check value for the GSP Flash memory (least significant byte first) The GSC performs a CRC check when R0.4 is set Once R0.4 is clear, R12 and R13 (16-bit lsb) contain an accurate CRC.

GSC_FIRMWARE_VER (Register R14): GSC Firmware Version

Bit	Description
0-7	Contains the GSC firmware version number

GSC_WRITE_PROTECT (Register R15): Write Protection

Bit	Name	Description
0	GSC_EEPROM_WP_ALL	1 = Write Protect all EEPROM regions
1	GSC_EEPROM_WP_BOARDINFO	1 = Write Protect the reserved Gateworks Board Info EEPROM section
2		Reserved
3-7	GSC_WP_PASSWD	Must be 0xB when altering bits[0:2] (ie write 0x59 (0xB<<3|0x1) to enable WP_ALL)

Code Examples

The following examples show how to utilize some of the GSC features and functions.

• Reading the GSC Registers
  • Use i2cget to read the GSC registers
    • i2cget -f -y BUS# DEVICE-ADDRESS# REGISTER#
    • For example, to read register 14:
      • i2cget -f -y 0 0x20 14
      • For the GSC, always use 0 and 0x20 for the BUS and DEVICE

• Board sleeping for 10 seconds
  • The following example will sleep the board for 10 seconds by setting the “add timer” to 10 seconds (from the current time) and then putting the board to sleep. This example uses the Linux I2C utilities.

    i2cset -f -y 0 0x20 6 10        ;# write add timer to 10sec
    i2cset -f -y 0 0x20 7 0
    i2cset -f -y 0 0x20 8 0
    i2cset -f -y 0 0x20 9 0
    i2cset -f -y 0 0x20 1 0x4       ;# set add time bit
    i2cset -f -y 0 0x20 1 0x3       ;# enable (put board to sleep)
    

The board will go to sleep and then wake up after 10 seconds. If you wanted the board to wakeup at a specific date/time regardless of the current RTC date/time you could set R2-5 to the number of seconds since the epoch (date +%s will show current system time in seconds) instead of using the R6-R9 'relative time' registers but note that if you set a value that has already passed you will have to activate the boards user pushbutton (if present) or remove the GSC battery for 10 seconds to reset the GSC/RTC to be able to wakeup the board.

• Reading GSC version
  • The following example will print out the GSC code revision. This example uses the Linux I2C utilities.

    i2cget -f -y 0 0x20 14          ;# read GSC revision from register 14
    0x16                            ;# hex revision value = v22
    

I2C communication with the GSC

The GSC communicates with the SoC via i2c at a maximum clock rate of 100KHz.

The v1 and v2 GSC (see above) may occasionally be busy and fail to ACK an i2c master transaction within the bit timing. The v3 GSC used in the Newport and newer product families is not susceptible to this.

Occasional I2C NAK's

I2C NAK's can occur on v1 and v2 GSC's. This is because every second the GSC performs a round of ADC conversions for its hardware monitoring function. At worst, you should never fail an ACK more than 2 times in a row based on the amount of time needed for the ADC conversions.

For this reason, you should retry and i2c read/write calls up to 3 times if the failure is a NAK (failure to ACK).

Note that the GSC registers are 8bit values where each bit has a different meaning. To read/modify/write you should do the following:

1. read register value
2. mask out the bits your going to clear (or set) (&= ~(mask))
3. set the bits your going to set

An example of how you can do this as well as check for i2c read/write errors using shell is the following:

R0=$(i2cget -f -y 0 0x20 0) && \
  R0=$((R0 & ~0x05)) && \
  R0=$((R0 |  0x04)) && \
  i2cset -f -y 0 0x20 0 $R0 || echo i2c error

• clear R0.0 (PB_HARD_RESET) to disable pushbutton hard reset
• set R0.2 (PB_SOFT_POWER) to enable soft power control
• Note that we are clearing bits 0 and 2 with R0 = R0 & ~0x05 and setting bits 2 with R0 = R0 | 0x04

GSC Drivers

A set of Linux drivers exists in the Gateworks BSP's that exposes some very useful GSC functionality:

• gsc-core driver
• gsc-watchdog driver
• gsc-input driver

GSC Core Linux kernel driver

The gsc-core driver provides the following:

• manages shared resources for the other GSC drivers
• interrupt controller to provide distinct interrupts for the various GSC status register bits (which other drivers can use)
• sysfs API for powering down the board (using the 'GSC sleep' function. Using a sleep time of 2 seconds guarantees a 1 to 2 second power-off)

Examples:

• power-cycle (2 seconds guarantees between 1 and 2 seconds power-off)

  sync && echo 2 > /sys/bus/i2c/devices/0-0020/powerdown
  

• power-down for 30 seconds:

  sync && echo 30 > /sys/bus/i2c/devices/0-0020/powerdown
  

GSC Watchdog kernel driver

Note that Newport boards do not need or use the GSC Watchdog (see above).

The gsc-wdt driver implements the Linux watchdog API for the hardware watchdog inside the GSC. When using this watchdog as opposed to the in-chip watchdog (ie mpcore for Laguna or imx for Ventana) the board will be fully power-cycled when/if the watchdog expires. This can be more reliable that SoC level resets which are done by the SoC watchdogs.

Note that the GSC watchdog function is available in GSC firmware v44 and beyond.

In order to use the GSC watchdog function and driver, the GSC watchdog must be manually enabled by the user - it is not enabled by default by the GSC firmware, and the GSC driver does not enable it.

The GSC watchdog driver init/probe function will fail if the GSC watchdog is not enabled. This allows the SoC watchdog driver to become /dev/watchdog0 if the GSC watchdog is not enabled.

To enable the GSC watchdog:

• in linux:

  i2cset -f -y 0 0x20 1 0x20 ;# enable for 30 second timeout
  # or
  i2cset -f -y 0 0x20 1 0x30 ;# enable for 60 second timeout
  

• in Ventana bootloader:

  gsc wd enable 30 # enable watchdog for 30s timeout
  # or
  gsc wd enable 60 # enable watchdog for 60s timeout
  

• in Laguna bootloader:

  i2c dev 0 && i2c mw 0x20 1 0x20 1 # set R1=0x20 to enable watchdog for 30s timeout
  # or
  i2c dev 0 && i2c mw 0x20 1 0x30 1 # set R1=0x30 to enable watchdog for 60s timeout
  

The following requirements exist for using the GSC watchdog with the GSC watchdog driver:

1. user manually enables the watchdog by setting GSC CTRL_1 bit 6 (see above)
2. GSC has v44 or newer firmware
3. GSC driver is enabled in the kernel (latest OpenWrt 14.08 BSP, Yocto v1.6+ BSP, Android Kitkat BSP)
4. a userspace app is tickling the proper watchdog (Note that if you have both in-chip cpu watchdog enabled and GSC watchdog enabled you will have two /dev/watchdog* devices - the SoC watchdog will be /dev/watchdog0 and the GSC watchdog will be /dev/watchdog1 in this case) (see below for BSP specific details)

BSP specific notes:

• OpenWrt 14.08+:
  • procd (PID1) takes on the responsibility of tickling the watchdog and does so at /dev/watchdog (not configurable without changing procd's watchdog.c code)
  • the GSC watchdog driver initializes before the SoC watchdog driver, so if you have met requirements 1-4 above, then the GSC watchdog device becomes /dev/watchdog (as opposed to the SoC watchdog). Failure to meet 1-4 above will result in the SoC watchdog becoming /dev/watchdog
  • you can tell procd to stop tickling the watchdog to test the affect:

    ubus call system watchdog '{ "stop": true }'  # system will reset when wd timeout occurs
    

• Yocto v1.6+:
  • The watchdog util is installed on the Gateworks BSP but not enabled. Therefore to meet requirement 4 above you must give it a conf file and configure it to start on boot (prior to enabling it):

    # create conf file
    cat << EOF > /etc/watchdog.conf
    watchdog-device = /dev/watchdog
    realtime = yes
    priority = 1
    interval = 5
    watchdog-timeout = 30
    EOF
    
    # create an init service script
    cat << EOF > /etc/init.d/watchdog
    #!/bin/sh
    
    watchdog
    EOF
    
    # make it executable
    chmod +x /etc/init.d/watchdog
    
    # configure as a system service to start on boot, priority 1
    update-rc.d watchdog defaults 1
    sync
    

• Android kk+:
  • The /dev/watchdog is enabled and tickled by /sbin/watchdogd which is kicked off from Android's init process and part of the Android init tool

Notes:

• see watchdog for more info

GSC Input kernel driver

The gsc-input driver registers itself as a handler for the interrupts that the gsc-core driver provides for the various interrupt sources of the GSC and dispatches Linux input events for each specific event.

All of these actions depend on the manual user configuration of the GSC CTRL_0 and GSC_IRQ_ENABLE registers. The driver does 'not' force a configuration upon the user. Note that all Gateworks Laguna and Ventana products ship with GSC_CTRL_0=0x01 configuring the pushbutton as a hard-reset and that this register is non-volatile as long as the GSC battery is powering the GSC. In such a default configuration a quick press/release of the user pushbutton will result in a hard reset instead of an interrupt that can be caught by software.

The following table shows what linux input EV_KEY event is sent for each interruptable configuration:

interrupt	key	event	requirements	notes
0	BTN_0	user button press/release within 700ms	R0.0=0 (hard reset disabled)	event fires appx 1s after the press
1	BTN_1	user eeprom section erased after 3x quick press/release	R0.0=0 (hard reset disabled) R0.1=1 (secure key enabled)	takes a couple of secs from first press to trigger as secure key is erased
2	BTN_2	user eeprom write-protect violation
4	BTN_3	gpio change	R0.0=0 (hard reset disabled)
5	BTN_4	tamper event	R0.5=1 (tamper detect enabled)
7	BTN_5	user button held >700ms	R0.6=1 (switch hold enabled)	event fires 700ms after press

• In addition to the requirements for GSC_CTRL_0 listed above, the associated bit in R11 corresponding to the interrupt number also must be enabled.

The driver does not alter the configuration of CTRL_0 so the user must do so manually depending on their interests. Some example configurations are:

• enable all events (allows catching individual button press and button release events):

  i2cset -f -y 0 0x20 0 0x00 # disable pushbutton hard reset
  i2cset -f -y 0 0x20 11 0xff # enable all interrupts
  

  • please see here regarding un-terminated inputs causing spurious GPIO_CHANGE events

BSP Specific notes:

• OpenWrt (14.08 and below only):
  • OpenWrt does not typically do anything with Linux input events. If you are interested in user pushbutton press-release events see pushbutton
  • you can use the event_test application to show Linux Input events:

    > event_test /dev/input/event0
    Input driver version is 1.0.1
    Input device ID: bus 0x0 vendor 0x0 product 0x0 version 0x0
    Input device name: "gsc_input"
    Supported events:
      Event type 0 (Reset)
        Event code 0 (Reset)
        Event code 1 (Key)
      Event type 1 (Key)
        Event code 256 (Btn0)
        Event code 257 (Btn1)
        Event code 258 (Btn2)
        Event code 259 (Btn3)
        Event code 260 (Btn4)
        Event code 261 (Btn5)
    Testing ... (interrupt to exit)
    Event: time 1435938985.047196, type 1 (Key), code 259 (Btn3), value 1
    Event: time 1435938985.047196, type 1 (Key), code 259 (Btn3), value 0
    Event: time 1435938985.047196, type 0 (Reset), code 0 (Reset), value 0
    Event: time 1435938985.047217, type 1 (Key), code 256 (Btn0), value 1
    Event: time 1435938985.047217, type 1 (Key), code 256 (Btn0), value 0
    Event: time 1435938985.047217, type 0 (Reset), code 0 (Reset), value 0
    

  • the above events occur when the user pushbutton is pressed and quickly released: Btn3 reflects the gpio change (IRQ_GPIO_CHANGE) event, and Btn0 reflects the pushbutton quick press-and-release event (IRQ_PB)
• Yocto:
  • you can use the evtest application to show Linux Input events:

    > evtest /dev/input/event0
    Input driver version is 1.0.1
    Input device ID: bus 0x0 vendor 0x0 product 0x0 version 0x0
    Input device name: "gsc_input"
    Supported events:
      Event type 0 (EV_SYN)
      Event type 1 (EV_KEY)
        Event code 256 (BTN_0)
        Event code 257 (BTN_1)
        Event code 258 (BTN_2)
        Event code 259 (BTN_3)
        Event code 260 (BTN_4)
        Event code 261 (BTN_5)
    Properties:
    Testing ... (interrupt to exit)
    Event: time 1435939364.644274, type 1 (EV_KEY), code 259 (BTN_3), value 1
    Event: time 1435939364.644274, type 1 (EV_KEY), code 259 (BTN_3), value 0
    Event: time 1435939364.644274, -------------- EV_SYN ------------
    Event: time 1435939364.644283, type 1 (EV_KEY), code 256 (BTN_0), value 1
    Event: time 1435939364.644283, type 1 (EV_KEY), code 256 (BTN_0), value 0
    Event: time 1435939364.644283, -------------- EV_SYN ------------
    

  • the above events occur when the user pushbutton is pressed and quickly released: Btn3 reflects the gpio change (IRQ_GPIO_CHANGE) event, and Btn0 reflects the pushbutton quick press-and-release event (IRQ_PB)
• Android:
  • a keymap file is present in /system/usr/keylayout/gsc_input.kl which maps the keys above to android key events. For example, the BTN_0 key (256 in Linux) is mapped to the POWER key for Android so that it acts like a power button toggle on a phone or tablet:

    > cat /system/usr/keylayout/gsc_input.kl
    # quick press-and-release (held <700ms) of front-panel pushbutton
    key 256   POWER                 WAKE
    
    # front panel pushbutton held >700ms (long-press)
    key 257   HOME                  WAKE
    
    # user-eeprom section erased after 3 quick presses
    key 258   SEARCH                WAKE
    
    # tamper event
    key 259   POWER                 WAKE
    

  • you can use the getevent application to show Linux Input events:

    > getevent /dev/input/event0
    0001 0103 00000001
    0001 0103 00000000
    0000 0000 00000000
    0001 0100 00000001
    0001 0100 00000000
    0000 0000 00000000
    

  • the above events occur when the user pushbutton is pressed and quickly released: Btn3 (hex 103) reflects the gpio change (IRQ_GPIO_CHANGE) event, and Btn0 (hex 100) reflects the pushbutton quick press-and-release event (IRQ_PB)

User Pushbutton Notes:

• If you need more flexibility in monitoring the GSC pushbutton (ie you want to determine if the button has been pressed and held down for 10 seconds) you need to monitor its GPIO manually. See pushbutton for more details on how to do this.

Reset Monitor

The third generation GSC used on the Newport product family acts as a hardware reset monitor for the board. For this feature the GSC monitors board-specific voltage rails before letting the CPU come out of reset.

GSC Updates

From time to time, there may be updates to this firmware in order to provide new features. There are two options for updating the GSC firmware:

• JTAG from a host Linux PC via the Linux jtag_usb application found ​here:

  jtag_usbv4 -m <firmware.txt>  ;# update GSC firmware image
  jtag_usbv4 -x <firmware.txt>  ;# verify GSC firmware image
  

• linux running on the target board using the gsc_update application which is present in the various Gateworks BSP's (source ​here)

  gsc_update -f <firmware.txt>
  

Notes:

• GSC firmware images can be found with the pre-built firmware images for the various product families
• using the gsc_update method, there is no validity checking of the firmware file (for transfer errors or for product ID) - updating an invalid image will require you to use the linux jtag_usbv4 application and a JTAG dongle to re-program (via ./jtag_usbv4 -m gsp_firmware.txt). Care should be taken to make sure you are updating a valid image meant for your target board. To verify the firmware update completed properly you can query the GSC firmware version register:

  i2cget -f -y 0 0x20 14
  

• after re-programming the GSC will revert some of its configuration just as if the coin-cell battery had been removed and replaced (see Battery Replacement info for details)

GSC Firmware Downloads:

• ​Newport Product Family
• ​Ventana Product Family
• ​Laguna Product Family
• ​Cambria Product Family
• ​Rincon Product Family

GSC Version History

The following represents the revision history for externally released GSC firmware revisions:

• v52: 20180518
  • GW630x:
    • add fan tach support
    • add power glitch protection
    • fix various power draw issues
    • fix PCA9555 emulation (pushbutton, tamper, WLAN disable)
      • improved the latency on GPIO_CHANGE events (from 1s max to 10ms max)
      • Note that this changed the Newport user pb gpio from P0.0 to P0.2 (device-tree change)
    • fixed VDD_VBATT calculation
• v51: 20180405
  • GW630x:
    • fix various power draw issues
    • fix issue with MCU_IRQ
    • convert to raw ADC's (ADCs now continually update instead of only at 1Hz)
    • add gsc-update support
    • fix issues causing occasional NAK's
• v50:
  • address an issue which could cause unexpected power draw from GSC battery from non-terminated inputs. This issue has been observed only on a small percentage of boards
• v49:
  • fix temperature accuracy between -40C and 0C
  • added Ventana GW553X support
  • added Newport GW630X support
• v48:
  • fix Ventana wake by pushbutton for GW5400
  • add ability to program 'firmware reset default' for R0 and R1 (see below)
• v47:
  • fix Ventana wake by pushbutton (boot_mode0 disabled if power control or wake)
• v46:
  • fix Ventana soft power control (boot_mode0 disabled when soft power control is enabled)
  • change: do a hard power cycle of board instead of reset on push-button press when hard reset enabled. This resolves some reset issues when using push-button reset on Ventana
• v45 - bugfix: fix occasional GSC reset during flash EEPROM write
• v44 - added GSC hardware watchdog
• v43 - Ventana bugfix:
  • fix Ventana boot recovery mode
  • fix hwmon readings at low temperatures
• v42 - added Ventana GW52XX/GW53XX support
• v41 - added Ventana GW51XX support
• v40 - added Ventana GW54XX support
• v39 - bugfix: fix possible race condition for missing i2c interrupts
• v38 - bugfix: fix race condition which can cause occasional boot failure
• v36 - add write protect capability and bugfix for missed bits if a start condition occurs during an ISR
• v35 - bugfix: resolve issue keeping board powered down if pushbutton pressed while board is off
• v34 - bugfix: wakeup board immediately if Wake time has already occurred in the past
• v33 - add support for GW2391
• v32 - pushbutton bugfix and change board power enable drive
• v30 - added mapping of pushbutton state in GPIO
• v29 - add support for PB_HOLD interrupt
• v28 - bugfix: resolve issue with detecting Tamper event while board powered on
• v27 - and 'Auto Switch' alternate boot device
• v23-26 - add support for new boards

Latest GSC revisions per baseboard:

family	board	revision
Newport	GW630x	​v52
Ventana	GW553x	​v50
	GW552x	​v50
	GW551x	​v50
	GW54xx	​v50
	GW53xx	​v50
	GW52xx	​v50
	GW51xx	​v50
Laguna	GW2391	​v50
	GW2388	​v50
	GW2387	​v50
	GW2383	​v50
	GW2382	​v50
	GW2380	​v50

GSC Version

Type the following command from the command prompt on the board. This will return a hex value:

i2cget -f -y 0 0x20 14

Battery / Battery Replacement

The coin cell battery used provides for approximately 3.8 years of battery-backed powered-off shelf life (see below). When primary board power is applied to the board (regardless of if the board is in 'sleep' mode) the battery source is not drained - this value is the worst-case life for an unpowered board.

Battery Replacement

Battery Replacement Details:

• A BR1225 coin cell battery is used.
• While primary board power is removed, the GSC battery can be removed for about 10 seconds before power is lost to the GSC. This gives you a small window of time to replace the battery without losing data such as RTC values. If longer then 10 seconds then the GSC will be reset.
• Laguna/Ventana (does not apply to Newport boards): If battery is replaced while board power is off, you must apply board power momentarily afterwards to reset the GSC into the proper operational state. If power is not applied the drain on the battery will be fairly large and will deplete the battery within about 3-4 weeks..
  • To verify the GSC current consumption, you can measure the voltage across a diode (+ probe on anode, - probe on cathode). The voltage across the diode with no power applied to the board should be approximately 300mV. If you see something in the 400mV range that means the GSC is not reset properly or there is some type of contamination causing excessive current draw. Contact support with your serial number for specifics on which diode ( support@… ).
• Note that bat rail voltage cannot be measured via Linux software as shown above until board power is turned off for one second or more (a second time when battery is replaced/GSC reset). When power is off, we monitor the bat voltage every 9 hours. When the board is fully powered on and booted into Linux, the bat reading cannot be continually updated and reports the last read voltage when the board was last powered off.
• The GSC can operate down to a battery voltage of 2.2V. If the battery goes below this erratic behavior can result and the battery should be either removed (operate without battery) or replaced.
• A fresh battery typically has a voltage ranging from 2.8 to 3.1V (also depends on temperature). The battery discharge rate is fairly flat but once it is discharged it can decay rapidly. Note that when the board is powered, the 3.3V power supply supplies power to the GSC and the battery will not be drained. This should be factored in when determining battery lifetime.
• The BR1225 coin cell is rated at 50mA/hours. Battery lifetime can be calculated by taking the battery rating divided by the current drain. The GSC's typical drain depends on the version:
  • v1/v2 (Laguna/Ventana): ~1.5uA: (50mA/hour)/(1.5uA) = 33.33K hours = 1388 days = 3.8 years
  • v3 (Newport): ~1.0uA: (50mA/hour)/(1.0uA) = 50K hours = 2083.3 days = 5.7 years

Firmware Reset Default conditions

The following items are reset if the battery is removed for more than 10 seconds or if the GSC firmware has been updated:

• RTC value (reset to 0 seconds since midnight Jan 1 1970)
• GSC configuration registers (R0's reset value varies from board to board, the others default to 0). Note that if using firmware v48 or later, you can program the 'firmware reset value' of R0 and R1 by writing to i2c eeprom slave 0x51 offset 0x50 and 0x51:

  # to set the default value of R0 to 0x04 (soft interrupt / soft power control)
  i2c dev 0 && i2c mw 0x51 0x50 0x04 1 # write 0x04 to 0x51:0x50
  # to set the default value of R1 to 0x30 to enable 60s watchdog
  i2c dev 0 && i2c mw 0x51 0x51 0x30 1 # write 0x30 to 0x51:0x51
  

• Fan controller registers default to the temperature setpoints shown in the Fan Controller section above
• Secure Key EEPROM area is set to 0xff's (see EEPROM section above)
• GPIO Port configuration is reset depending on particular board:
  • All general purpose I/O's are set to 'inverted inputs' (with pullup enabled)
  • All dedicated outputs are set to output high
  • All dedicated inputs are configured as inputs*

Board Storage with respect to Battery

When a board is powered on, the GSC will draw power from the primary power supply and not it's coincell battery.

However, when the board sits on a shelf with no Vin applied, the GSC is still running its application and consuming very little power such that the battery should last approximately 3.8 years. This approximation will vary based on environmental conditions such as temperature. (see ​datasheet).

Care should be taken that the board is stored in a way that the battery case (which is the + side of the battery) does not come in contact with a conductive path to ground on the board as doing so would not only drain the battery but if this conduction path persists for ~8 seconds or more it would put the GSC into 'reset' where its current path (even after the battery short is removed) is higher than normal. This is the same scenario described above in the Battery replacement section and can be resolved by powering the board on at least once to get the GSC out of reset.